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2025-05-12target/i386/emulate: mostly rewrite flags handlingPaolo Bonzini3-125/+84
While Bochs's algorithms are pretty solid, there are small opportunities to improve them or to make their logic more similar to TCG's handling of condition codes. - use a single bit for the difference between bits 0..7 of result and PF. This is useful because "set only ZF" is not a common case. - place SD in the same place as SF - move CF and PO at bits 62 and 63 when target_ulong is 64-bits wide, so that 64-bit ALU operations need fewer shifts - use rotates to move CF and AF from auxbits to their eflags position Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-12target/i386/emulate: stop overloading decode->op[N].ptrPaolo Bonzini4-101/+109
decode->op[N].ptr can contain either a host pointer (!) in CPUState or a guest virtual address. Pass the whole struct to read_val_ext and write_val_ext, so that it can decide the contents based on the operand type. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-12target/i386: implement TSS trap bitPaolo Bonzini1-4/+5
Now that we can do so after the error code has been pushed, raising the #DB exception for task-switch traps is trivial. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-12target/i386: move push of error code to switch_tss_raPaolo Bonzini1-31/+41
Move it there so that it can be done before the TSS trap bit is processed. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-12target/i386: list TCG-supported features for CPUID[80000021h].EAXPaolo Bonzini1-1/+12
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-12target/i386: ignore misplaced REX prefixesPaolo Bonzini1-9/+27
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-09Merge tag 'hw-misc-20250508' of https://github.com/philmd/qemu into stagingStefan Hajnoczi4-4/+4
Misc HW patches - Allow using plugins on BSD user-emulation - Inline VMSTATE_CPU() macro - Fix header includes for HVF x86 - Build hw/hyperv/ files once - Various typo fixed - Fix issue in i.MX I2C model # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmgco7IACgkQ4+MsLN6t # wN5b/RAAvI+0Fyo/QNTjUQKBsFT7M9DY2bv2rxElG5+gwQvrqRkwV4POjJ42TFbl # NazNnywIW2eZvjQ1W3pBceiAhXAOxRi/zSTRO30uhL0DFmfAIEF6aMZdVZKg01mq # U/x5WF3WM8taXYE5V8kgV+Rr6b02SMGgtUcNVTnDjVdmRI0+ByPf122IwniKffhR # kJhPj4tgU/wBsOisgPTAr1kbQePyvbvckxKc1kt73jPRV6fUtVV14qcrBN6zECV3 # +uFit6Q/zYH21XpFdq/3X9lEjMZNGI6zBZ939/x5Bpj53MjmYovYY81987ioAB7S # zsmFZ2Nl7L/8l/jKrhKPS+l71OzmLI1dMzr2CrOxgMhXxfItta9y04CLDf7ZXSf6 # mgDE3rA89C33dzoGnb4axphmcposyM/u0lLhGgnMh3GFv84P6/DqgxKZv8vj6OMq # U/DhHPw507W/JAg8ge/5YchVJwxKfBbHm0y7NLqH1IGmoyyqsMQo6DbC9/zTK7T4 # dAZdcrm2dBbSxYaL5J8gTGPo/QjVG9BaU9EvKIcZf181QSHg//QCYB6iN5Phx5hO # KH9hUTmpqA4Lza0XGGUM1c43/24Dq/i1I0EncW4zqFqaf9l9M06i5cdQrU+myzAs # O/dLsFlm7WAJLDkt2Ax2peYKHVKpGywFRsCR04uulkoLoD5nd/w= # =1VOP # -----END PGP SIGNATURE----- # gpg: Signature made Thu 08 May 2025 08:29:38 EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20250508' of https://github.com/philmd/qemu: hw/i2c/imx: Always set interrupt status bit if interrupt condition occurs hw/i386/acpi-build: Fix typo and grammar in comment hw/i386/acpi-build: Update document reference hw/i386/acpi-build: Fix build_append_notfication_callback typo hw/acpi/ged: Fix wrong identation hw/pci/pcie_port: Fix pcie_slot_is_hotpluggbale_bus typo hw/hyperv/hyperv: common compilation unit hw/hyperv/hyperv_testdev: common compilation unit hw/hyperv/balloon: common balloon compilation units hw/hyperv/syndbg: common compilation unit hw/hyperv/vmbus: common compilation unit hw/hyperv/hyperv.h: header cleanup hw/hyperv/hv-balloon-stub: common compilation unit system/hvf: Expose hvf_enabled() to common code system/hvf: Avoid including 'cpu.h' accel/hvf: Include missing 'hw/core/cpu.h' header target/migration: Inline VMSTATE_CPU() qom: Factor qom_resolve_path() out bsd-user: add option to enable plugins Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-08target/migration: Inline VMSTATE_CPU()Philippe Mathieu-Daudé4-4/+4
VMSTATE_CPU() is only used in 4 places and doesn't provide much, directly inline it using VMSTATE_STRUCT(). This removes the last COMPILING_PER_TARGET in "hw/core/cpu.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Peter Xu <peterx@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250429085148.11876-1-philmd@linaro.org>
2025-05-07Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi6-11/+16
* ci: enable RISC-V cross jobs * rust: bump minimum supported version to 1.77 * rust: enable uninlined_format_args lint * initial Emscripten support * small fixes # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmgaFq8UHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOxAAf/YPKw5KAoE5SwUqJ0oSOMHrU0w4jc # A2Qiw1uziA6kDmUMUXwWR7Qbd8V7jtihGrgTrIPopeavgWWQeNsBHjN4WxHRI7aq # +429rjzFo9V9tSfgp6UcLQSk/9kC4ygEwPnesHpKd27fS6z9Wg4AQkj1iFipR179 # wC3fqwOqqWZSjfUd7wjo7McFYZgL5j/cxmFXePh8+fdT+6PUKdG9nRW86KUPDZ+A # 8HxcuOW7GZd+LhnYUhi7vlLFo/RgVsGQWj0Q4BDJvUkKa13t9UUCGff7uQP2AC3v # ny0gWDcmbWY1L/QXyNzhgd44X4LAjCmpnonlYnrdZizEmhv3aByd+fANgw== # =uIJK # -----END PGP SIGNATURE----- # gpg: Signature made Tue 06 May 2025 10:03:27 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (30 commits) gitlab: Enable CI for wasm build tests: Add Dockerfile containing dependencies for Emscripten build meson: Add wasm build in build scripts util: Add coroutine backend for emscripten util: exclude mmap-alloc.c from compilation target on Emscripten Disable options unsupported on Emscripten include/qemu/osdep.h: Add Emscripten-specific OS dependencies block: Fix type conflict of the copy_file_range stub block: Add including of ioctl header for Emscripten build util/cacheflush.c: Update cache flushing mechanism for Emscripten include/glib-compat.h: Poison g_list_sort and g_slist_sort target/s390x: Fix type conflict of GLib function pointers target/ppc: Fix type conflict of GLib function pointers target/i386/cpu.c: Fix type conflict of GLib function pointers target/arm/helper.c: Fix type conflict of GLib function pointers docs: build-system: fix typo ci: run RISC-V cross jobs by default rust: clippy: enable uninlined_format_args lint target/i386/emulate: fix target_ulong format strings docs: rust: update for newer minimum supported version ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-07Merge tag 'pull-target-arm-20250506' of ↵Stefan Hajnoczi6-87/+70
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm/npcm8xx_boards: Correct valid_cpu_types setting of NPCM8XX SoC * arm/hvf: fix crashes when using gdbstub * target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debug * hw/arm/virt: Remove deprecated old versions of 'virt' machine * tests/functional: Add test for imx8mp-evk board with USDHC coverage * hw/arm: Attach PSPI module to NPCM8XX SoC * target/arm: Don't assert() for ISB/SB inside IT block * docs: Don't define duplicate label in qemu-block-drivers.rst.inc * target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGET * hw/pci-host/designware: Fix viewport configuration * hw/gpio/imx_gpio: Fix interpretation of GDIR polarity # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmgaH50ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3l4ED/0QOV6oev1ILqA1INBjY7Ct # VrjzjsynFnUkyU0MLKyuK+mBRYmeR1OWtIRTkbgIsRA23XqV4de/BhGsVCGrRA0r # VS/hV2kTQM0GYU2dCr9LpOC3jX0dDzft5uW9GjW/sW9infAwXRwKhGgkIV6q/G5V # Y6cMN7UXrOnomF8Spk5VvK8HH9OHV/fuSlWenk9X1bXPpVQ3jymqZ1eRSDXOzDdM # uP6lVdI3oHCpRPeXKa1EA8cfQa9M/y9XSzDIrF8OTZKVcIzbX8/XR+y74e4UMIvK # DD3nAuAXcezy3286Pu7OfciRBJfq3eFHZVXOKfQWFI3MStPmexKqoHm8JtQxXJOT # uJdaugItLahlPtNk41nAydYzYimK/MBKCWAfTqecEhZ9Cd64jeOPM9zXwRkXwyuu # n9XQUhm5Ll22urd4q2M8cCxKBP2OoaEBFS4Hn9uDpVDcWpRMLe2DP7ywzZjdLU9b # jLSlana5+wpMuwIasXlNzWgT37RA+xlDE2Snaz7K/Z3JV/XNZAZD6WXV72zTzhFs # EI10edHI+JXXlbT1Ev/yVv4cN9h/Kr3hyoOKat2ySaomW26H27wNPuvPTto4rCYU # 6VQJmJvwPSBWELI5eRbcN269K0ar1UXUsvDsy97cq35me3gFvfAZFksLpnPWKef6 # pvwwPuxLWQXs+chepuQyXA== # =c21p # -----END PGP SIGNATURE----- # gpg: Signature made Tue 06 May 2025 10:41:33 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250506' of https://git.linaro.org/people/pmaydell/qemu-arm: (32 commits) hw/arm/virt: Remove deprecated virt-4.0 machine hw/arm/virt: Remove deprecated virt-3.1 machine hw/arm/virt: Remove deprecated virt-3.0 machine hw/arm/virt: Update comment about Multiprocessor Affinity Register hw/gpio/imx_gpio: Fix interpretation of GDIR polarity hw/pci-host/designware: Fix viewport configuration hw/pci-host/designware: Remove unused include target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGET docs: Don't define duplicate label in qemu-block-drivers.rst.inc target/arm: Don't assert() for ISB/SB inside IT block hw/arm: Attach PSPI module to NPCM8XX SoC tests/functional: Add test for imx8mp-evk board with USDHC coverage hw/arm/virt: Remove VirtMachineClass::no_highmem_ecam field hw/arm/virt: Remove deprecated virt-2.12 machine hw/arm/virt: Remove VirtMachineClass::smbios_old_sys_ver field hw/arm/virt: Remove deprecated virt-2.11 machine hw/arm/virt: Remove deprecated virt-2.10 machine hw/arm/virt: Remove deprecated virt-2.9 machine hw/arm/virt: Remove VirtMachineClass::claim_edge_triggered_timers field hw/arm/virt: Remove deprecated virt-2.8 machine ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-06Merge tag 'pull-tcg-20250501-v2' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi173-710/+620
include: Remove 'exec/exec-all.h' accel/tcg: Build tb-maint.c twice accel/tcg: Build cpu-exec.c twice accel/tcg: Build translate-all.c twice accel/tcg: Build tcg-all.c twice accel/tcg: Build cputlb.c once accel/tcg: Build user-exec.c once # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmgZFdYdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/8RAf8C2NTtUNlBrjtPrQD # hP2YiNVfI+c9e3x3Bivx++9YUYfynWyPO774axnyhqYg3cJONWs+4HJ/MQHNSG/G # qT+7EihGIDwnjWxTvu9wp5XucvaGKBqGEQ2IZrr0JBEnvrrpuhiauqP7Bjb37eAj # kxw50NUxxz4wqk5Ql4UZyJ0h1peH5PFNr9uozhr6HJSEET7GxPMfUy611jAa/eXc # MDkiDwd+0JGSKkMSQaCocMO2vL4OQGr3sTBNHQZ/RalEdMp+AJiQgjJ0fFfCInwK # 4w8/8we8MKUBIwTn5kTUBjPrI7nlhJk5mFm5aV7fNvSClGf5Yb62SfPesQKm5qkE # z3aApA== # =Lpyu # -----END PGP SIGNATURE----- # gpg: Signature made Mon 05 May 2025 15:47:34 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250501-v2' of https://gitlab.com/rth7680/qemu: (59 commits) accel/tcg: Build user-exec.c once accel/tcg: Avoid abi_ptr in user-exec.c accel/tcg: Remove TARGET_PAGE_DATA_SIZE accel/tcg: Move TARGET_TAGGED_ADDRESSES to TCGCPUOps.untagged_addr include/user: Use vaddr in guest-host.h include/user: Convert GUEST_ADDR_MAX to a variable accel/tcg: Build cputlb.c once accel/tcg: Use vaddr for plugin_{load,store}_cb accel/tcg: Use target_long_bits() in cputlb.c accel/tcg: Move tlb_vaddr_to_host declaration to probe.h accel/tcg: Move user-only tlb_vaddr_to_host out of line accel/tcg: Use vaddr in cpu_loop.h accel/tcg: Build tcg-all.c twice accel/tcg: Build translate-all.c twice accel/tcg: Use target_long_bits() in translate-all.c accel/tcg: Don't use TARGET_LONG_BITS in decode_sleb128 tcg: Define INSN_START_WORDS as constant 3 qemu: Introduce target_long_bits() qemu/target_info: Add %target_cpu_type field to TargetInfo system/vl: Filter machine list available for a particular target binary ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-06target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGETPeter Maydell3-53/+9
Our KVM code includes backwards compatibility support for ancient kernels which don't support the KVM_ARM_PREFERRED_TARGET ioctl. This ioctl was introduced in kernel commit 42c4e0c77ac91 in September 2013 and is in v3.12, so it's reasonable to assume it's present. (We already dropped support for kernels without KVM_CAP_DEVICE_CTRL, a feature added to the kernel in April 2013, in our commit 84f298ea3e; so there are only about six months' worth of kernels, from v3.9 to v3.11, that we don't already fail to run on and that this commit is dropping handling for.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250318114222.1018200-1-peter.maydell@linaro.org
2025-05-06target/arm: Don't assert() for ISB/SB inside IT blockPeter Maydell1-1/+2
If the guest code has an ISB or SB insn inside an IT block, we generate incorrect code which trips a TCG assertion: qemu-system-arm: ../tcg/tcg-op.c:3343: void tcg_gen_goto_tb(unsigned int): Assertion `(tcg_ctx->goto_tb_issue_mask & (1 << idx)) == 0' failed. This is because we call gen_goto_tb(dc, 1, ...) twice: brcond_i32 ZF,$0x0,ne,$L1 add_i32 pc,pc,$0x4 goto_tb $0x1 exit_tb $0x73d948001b81 set_label $L1 add_i32 pc,pc,$0x4 goto_tb $0x1 exit_tb $0x73d948001b81 Both calls are in arm_tr_tb_stop(), one for the DISAS_NEXT/DISAS_TOO_MANY handling, and one for the dc->condjump condition-failed codepath. The DISAS_NEXT handling doesn't have this problem because arm_post_translate_insn() does the handling of "emit the label for the condition-failed conditional execution" and so arm_tr_tb_stop() doesn't have dc->condjump set. But for DISAS_TOO_MANY we don't do that. Fix the bug by making arm_post_translate_insn() handle the DISAS_TOO_MANY case. This only affects the SB and ISB insns when used in Thumb mode inside an IT block: only these insns specifically set is_jmp to TOO_MANY, and their A32 encodings are unconditional. For the major TOO_MANY case (breaking the TB because it would cross a page boundary) we do that check and set is_jmp to TOO_MANY only after the call to arm_post_translate_insn(); so arm_post_translate_insn() sees is_jmp == DISAS_NEXT, and we emit the correct code for that situation. With this fix we generate the somewhat more sensible set of TCG ops: brcond_i32 ZF,$0x0,ne,$L1 set_label $L1 add_i32 pc,pc,$0x4 goto_tb $0x1 exit_tb $0x7c5434001b81 (NB: the TCG optimizer doesn't optimize out the jump-to-next, but we can't really avoid emitting it because we don't know at the point we're emitting the handling for the condexec check whether this insn is going to happen to be a nop for us or not.) Cc: qemu-stable@nongnu.org Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2942 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250501125544.727038-1-peter.maydell@linaro.org
2025-05-06target/s390x: Fix type conflict of GLib function pointersKohei Tokunaga1-2/+2
On Emscripten, function pointer casts can result in runtime failures due to strict function signature checks. This affects the use of g_list_sort and g_slist_sort, which internally perform function pointer casts that are not supported by Emscripten. To avoid these issues, g_list_sort_with_data and g_slist_sort_with_data should be used instead, as they do not rely on function pointer casting. Signed-off-by: Kohei Tokunaga <ktokunaga.mail@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Link: https://lore.kernel.org/r/e91c4e266b839f62b5c41173a05896b210ae1180.1745820062.git.ktokunaga.mail@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-06target/ppc: Fix type conflict of GLib function pointersKohei Tokunaga1-2/+2
On Emscripten, function pointer casts can result in runtime failures due to strict function signature checks. This affects the use of g_list_sort and g_slist_sort, which internally perform function pointer casts that are not supported by Emscripten. To avoid these issues, g_list_sort_with_data and g_slist_sort_with_data should be used instead, as they do not rely on function pointer casting. Signed-off-by: Kohei Tokunaga <ktokunaga.mail@gmail.com> Link: https://lore.kernel.org/r/d917055d35f5ff7316ccdcbdf57af9a7bd85bf29.1745820062.git.ktokunaga.mail@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-06target/i386/cpu.c: Fix type conflict of GLib function pointersKohei Tokunaga1-3/+8
On Emscripten, function pointer casts can result in runtime failures due to strict function signature checks. This affects the use of g_list_sort and g_slist_sort, which internally perform function pointer casts that are not supported by Emscripten. To avoid these issues, g_list_sort_with_data and g_slist_sort_with_data should be used instead, as they do not rely on function pointer casting. Signed-off-by: Kohei Tokunaga <ktokunaga.mail@gmail.com> Link: https://lore.kernel.org/r/8ee6c2b02c97d5db358c3eb290d00afe71d1ceb7.1745820062.git.ktokunaga.mail@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-06target/arm/helper.c: Fix type conflict of GLib function pointersKohei Tokunaga1-2/+2
On Emscripten, function pointer casts can result in runtime failures due to strict function signature checks. This affects the use of g_list_sort and g_slist_sort, which internally perform function pointer casts that are not supported by Emscripten. To avoid these issues, g_list_sort_with_data and g_slist_sort_with_data should be used instead, as they do not rely on function pointer casting. Signed-off-by: Kohei Tokunaga <ktokunaga.mail@gmail.com> Link: https://lore.kernel.org/r/7d56c82382e8b4f1694b6d7883b2ce3084fdc72d.1745820062.git.ktokunaga.mail@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-06target/i386/emulate: fix target_ulong format stringsPaolo Bonzini2-2/+2
Do not assume that TARGET_FMT_lx is %llx. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-06target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debugPierrick Bouvier1-1/+21
It was reported that QEMU monitor command gva2gpa was reporting unmapped memory for a valid access (qemu-system-aarch64), during a copy from kernel to user space (__arch_copy_to_user symbol in Linux) [1]. This was affecting cpu_memory_rw_debug also, which is used in numerous places in our codebase. After investigating, the problem was specific to arm_cpu_get_phys_page_attrs_debug. When performing user access from a privileged space, we need to do a second lookup for user mmu idx, following what get_a64_user_mem_index is doing at translation time. [1] https://lists.nongnu.org/archive/html/qemu-discuss/2025-04/msg00013.html Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250414153027.1486719-5-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06target/arm/ptw: extract arm_cpu_get_phys_pagePierrick Bouvier1-10/+14
Allow to call that function easily several times in next commit. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250414153027.1486719-4-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06target/arm/ptw: get current security_space for current mmu_idxPierrick Bouvier1-1/+1
It should be equivalent to previous code. Allow to call common function to get a page address later. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250414153027.1486719-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06target/arm/ptw: extract arm_mmu_idx_to_security_spacePierrick Bouvier1-7/+14
We'll reuse this function later. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250414153027.1486719-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hvf: avoid repeatedly setting trap debug for each cpuMads Ynddal1-16/+11
hvf_arch_set_traps is already called from a context of a specific CPUState, so we don't need to do a nested CPU_FOREACH. It also results in an error from hv_vcpu_set_sys_reg, as it may only be called from the thread owning the vCPU. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2895 Tested-by: Daniel Gomez <da.gomez@samsung.com> Signed-off-by: Mads Ynddal <m.ynddal@samsung.com> Reported-by: Daniel Gomez <da.gomez@samsung.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250402135229.28143-2-mads@ynddal.dk Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-05accel/tcg: Remove TARGET_PAGE_DATA_SIZERichard Henderson2-6/+2
This macro is used by only one target, and even then under unusual conditions -- AArch64 with mmap's PROT_MTE flag. Since page size for aarch64-linux-user is variable, the per-page data size is also variable. Since page_reset_target_data via target_munmap does not have ready access to CPUState, simply pass in the size from the first allocation and remember that. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05accel/tcg: Move TARGET_TAGGED_ADDRESSES to TCGCPUOps.untagged_addrRichard Henderson3-38/+28
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi4-25/+30
* rust: support migration of HPET device * target/i386/hvf: fix compilation errors * target/i386/tcg: fix some interrupt shadow cases * hw/char/serial: remove unused prog_if compat property * rust: centralize config in workspace root * monitor: fix race on exiting QEMU # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmgVQzkUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOR8Af/Tke7kRZQyvoKURaKpVOBgP91fTQu # IKwmX1OYe9JMPBwZV5g/++2HSaAddDzkFq90gmgTY+hpvRE3kDWOA86QtDRP4LKa # Oq3yW48yrFiRZBAxERgRxRCsEvzlPC3cAEqCQd4fTL+cW6NVorbj4x/tQcALb47V # cgXXVp59TW4lJk7nJUjd0mCFK1qEoIbZuuBgMn32K+fpBV/UghcoImT2giMeM24Y # WW3olrLA9UN2fh5da7923WUvA9mSjnE0Yfdk6eKC3nCzlgMKktofwKHilm0tA6xA # 7sJbwYTDSB9QxgnNw3WvAFAOMapJmedaSNorZdmcxCss7ed0s8hV8am9vQ== # =LFS/ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 02 May 2025 18:12:09 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: monitor: don't wake up qmp_dispatcher_co coroutine upon cleanup rust: centralize config in workspace root hw/char/serial: Remove unused prog_if compat property target/i386: do not block singlestep for STI target/i386: do not trigger IRQ shadow for LSS target/i386/hvf: fix a compilation error target/i386/emulate: remove rflags leftovers rust/hpet: Support migration rust/timer: Define NANOSECONDS_PER_SECOND binding as u64 rust/vmstate_test: Test varray with num field wrapped in BqlCell rust: assertions: Support index field wrapped in BqlCell vmstate: support varray for vmstate_clock! rust/vmstate: Add support for field_exists checks Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-05Merge tag 'pull-request-2025-04-30' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi2-30/+62
staging * Extend s390x diagnose call 308 subcode 10 to return more information * Make valgrind support configurable * Drop support for Python 3.8 * Some other misc cosmetic changes # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmgScIQRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbXf+hAAnt6RcceX8e9CSXaggozXMeI5c/7nMUJl # PTJrWV0HXhspKR2SEYADkKk5cVGWnSum7PDgrwHXMyykUSE2jOsUhIrWauyLaiuE # fKIOhTOX6DiYPINVJzsJ8JXrJ7jkYmnGMnrbZg1i1wnYwx9ZkAAZOagGu4pMguml # digEVMJp7KiGztCrQwA/Og1zrTTPP9a6071tCvungQJDMrLuJgYb+hafpoNBaAy3 # WoOqP/Fh5AXHkySZlKGhL/mqrj7FVSUMWsNoBncZXtTcnnSP4u6gVt0fd7W9LC6u # QGGGTEV8UkRhiW4s/Dxd6HOt0OS9m4sDWbubYv9nzIfRM1X8rfKqOCnjKxbeU/lI # kdoZpK1FSyzKcH+QvEVYaQv33BitVrx3h+WQKgSCZTmTit9TjshBAEDAvzfL6oML # xYM4oqf0kWqlJjIfatx11dfLJLpAwk8jtgKz9iSPH11lLqGQmsdPNMEdXvUiuiSZ # tddvuKn0AKwTNO+OWonztBO2aiADSO9hZhWAPVuZUTYCt9zWyQF4ddAgOm2+FZOg # B9u01aBNSodTaBFASDabWnoi/09lPuhcqINB18XJXG3EsdbrtTP9PjHkSL8Oj+eA # v2g+uuxIlD3OfvTdrRAVpRjrGBcz3yKkPOw4KA/pnCyP/w3SnoObu0GjFcD4Okuk # pfvd8eAw7dI= # =K0wD # -----END PGP SIGNATURE----- # gpg: Signature made Wed 30 Apr 2025 14:48:36 EDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2025-04-30' of https://gitlab.com/thuth/qemu: docs/devel/build-environment: enhance MSYS2 instructions hw/rtc/mc146818rtc: Drop pre-v3 migration stream support meson.build: Put the D-Bus summary into the UI section tests/functional/test_ppc64_pseries: Skip test_ppc64_linux_smt_boot if necessary Drop support for Python 3.8 meson/configure: add 'valgrind' option & --{en, dis}able-valgrind flag target/s390x: Return UVC cmd code, RC and RRC value when DIAG 308 Subcode 10 fails to enter secure mode target/s390x: Introduce function when exiting PV target/s390x: Introduce constant when checking if PV header couldn't be decrypted Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-02target/i386: do not block singlestep for STIPaolo Bonzini1-1/+5
STI will trigger a singlestep exception even if it has inhibit-IRQ behavior. Do not suppress single-step for all IRQ-inhibiting instructions, instead special case MOV SS and POP SS. Cc: qemu-stable@nongnu.org Fixes: f0f0136abba ("target/i386: no single-step exception after MOV or POP SS", 2024-05-25) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-02target/i386: do not trigger IRQ shadow for LSSPaolo Bonzini2-13/+18
Because LSS need not trigger an IRQ shadow, gen_movl_seg can't just use the destination register to decide whether to inhibit IRQs. Add an argument. Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-02target/i386/hvf: fix a compilation errorWei Liu1-0/+1
Include exec/target_page.h to fix the following build error. x86_64-softmmu.a.p/target_i386_hvf_hvf.c.o -c ../target/i386/hvf/hvf.c ../target/i386/hvf/hvf.c:139:49: error: use of undeclared identifier 'TARGET_PAGE_SIZE' 139 | uint64_t dirty_page_start = gpa & ~(TARGET_PAGE_SIZE - 1u); | ^ ../target/i386/hvf/hvf.c:141:45: error: use of undeclared identifier 'TARGET_PAGE_SIZE' 141 | hv_vm_protect(dirty_page_start, TARGET_PAGE_SIZE, | ^ Signed-off-by: Wei Liu <wei.liu@kernel.org> Link: https://lore.kernel.org/r/aBBws1ikCDfyC0RI@liuwe-devbox-ubuntu-v2.tail21d00.ts.net Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-02target/i386/emulate: remove rflags leftoversMagnus Kulke1-11/+6
Fixes: c901905ea670 ("target/i386/emulate: remove flags_mask") In c901905ea670 rflags have been removed from `x86_decode`, but there were some leftovers. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20250429093319.5010-1-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-01tcg: Define INSN_START_WORDS as constant 3Richard Henderson2-2/+2
Use the same value for all targets. Rename TARGET_INSN_START_WORDS and do not depend on TARGET_INSN_START_EXTRA_WORDS. Remove TCGContext.insn_start_words. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Split out accel/tcg/helper-retaddr.hRichard Henderson5-0/+5
Move set_helper_retaddr and clear_helper_retaddr to a new header file. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOpsRichard Henderson24-20/+45
Move the global function name to a hook on TCGCPUOps. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_stateRichard Henderson19-136/+174
Combine 3 different pointer returns into one structure return. Include a cflags field in TCGTBCPUState, not filled in by cpu_get_tb_cpu_state, but used by all callers. This fills a hole in the structure and is useful in some subroutines. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30target/riscv: Move cpu_get_tb_cpu_state to tcg-cpu.cRichard Henderson2-97/+98
This function is only relevant to tcg. Move it to a tcg-specific file. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30target/arm: Unexport assert_hflags_rebuild_correctlyRichard Henderson3-7/+1
This function is no longer used outside of hflags.c. We can remove the stub as well. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30target/arm: Move cpu_get_tb_cpu_state to hflags.cRichard Henderson2-110/+110
This is a tcg-specific function, so move it to a tcg file. Also move mve_no_pred, a static function only used within cpu_get_tb_cpu_state. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Hoist cpu_get_tb_cpu_state decl to accl/tcg/cpu-ops.hRichard Henderson36-285/+240
For some targets, simply remove the local definition. For other targets, move the inline definition out of line. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30target/i386: Split out x86_cpu_exec_resetRichard Henderson1-1/+10
Note that target/i386/cpu.h defines CPU_INTERRUPT_INIT as CPU_INTERRUPT_RESET. Therefore we can handle the new TCGCPUOps.cpu_exec_reset hook. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Introduce TCGCPUOps.cpu_exec_resetRichard Henderson19-0/+19
Initialize all instances with cpu_reset(), so that there is no functional change. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30include: Remove 'exec/exec-all.h'Philippe Mathieu-Daudé137-137/+0
"exec/exec-all.h" is now fully empty, let's remove it. Mechanical change running: $ sed -i '/exec\/exec-all.h/d' $(git grep -wl exec/exec-all.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-14-philmd@linaro.org>
2025-04-30accel/tcg: Extract probe API out of 'exec/exec-all.h'Philippe Mathieu-Daudé19-0/+19
Declare probe methods in "accel/tcg/probe.h" to emphasize they are specific to TCG accelerator. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-13-philmd@linaro.org>
2025-04-30accel/tcg: Include 'accel/tcg/getpc.h' in 'exec/helper-proto'Philippe Mathieu-Daudé1-1/+0
Most files including "exec/helper-proto.h" call GETPC(). Include it there (in the common part) instead of the unspecific "exec/exec-all.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-10-philmd@linaro.org>
2025-04-30target/riscv: Include missing 'accel/tcg/getpc.h' in csr.cPhilippe Mathieu-Daudé1-0/+1
"accel/tcg/getpc.h" is pulled in indirectly. Include it explicitly to avoid when refactoring unrelated headers: target/riscv/csr.c:2117:25: error: call to undeclared function 'GETPC' [-Wimplicit-function-declaration] 2117 | if ((val & RVC) && (GETPC() & ~3) != 0) { | ^ Note the TODO comment around GETPC() added upon introduction in commit f18637cd611 ("RISC-V: Add misa runtime write support"): 2099 static RISCVException write_misa(CPURISCVState *env, int csrno, 2100 target_ulong val) 2101 { ... 2113 /* 2114 * Suppress 'C' if next instruction is not aligned 2115 * TODO: this should check next_pc 2116 */ 2117 if ((val & RVC) && (GETPC() & ~3) != 0) { 2118 val &= ~RVC; 2119 } Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-8-philmd@linaro.org>
2025-04-30accel/tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smcRichard Henderson4-6/+2
Instead of having a compile-time TARGET_HAS_PRECISE_SMC definition, have each target set the 'precise_smc' field in the TCGCPUOps structure. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Add CPUState arg to tb_invalidate_phys_rangeRichard Henderson1-1/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30target/s390x: Return UVC cmd code, RC and RRC value when DIAG 308 Subcode 10 ↵Gautam Gala2-22/+55
fails to enter secure mode Extend DIAG308 subcode 10 to return the UVC RC, RRC and command code in bit positions 32-47, 16-31, and 0-15 of register R1 + 1 if the function does not complete successfully (in addition to the previously returned diag response code in bit position 47-63). Reviewed-by: Janosch Frank <frankja@linux.ibm.com> Signed-off-by: Gautam Gala <ggala@linux.ibm.com> Reviewed-by: Steffen Eiden <seiden@linux.ibm.com> Message-ID: <20250423080915.1048123-4-ggala@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-04-30target/s390x: Introduce function when exiting PVGautam Gala1-8/+6
Replace an existing macro (s390_pv_cmd_exit) that looks like a function with an actual function. The function will be used when exiting PV instead of the macro. Reviewed-by: Steffen Eiden <seiden@linux.ibm.com> Reviewed-by: Janosch Frank <frankja@linux.ibm.com> Signed-off-by: Gautam Gala <ggala@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250423080915.1048123-3-ggala@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-04-30target/s390x: Introduce constant when checking if PV header couldn't be ↵Gautam Gala1-1/+2
decrypted Introduce a named constant when checking the Set Secure Configuration parameters UV call return code for the case where no valid host key was found and therefore the PV header couldn't be decrypted (0x108). Reviewed-by: Steffen Eiden <seiden@linux.ibm.com> Reviewed-by: Janosch Frank <frankja@linux.ibm.com> Signed-off-by: Gautam Gala <ggala@linux.ibm.com> Message-ID: <20250423080915.1048123-2-ggala@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
generated by cgit v1.1 at 2025-09-20 22:10:14 +0000