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2025-05-28qapi: expose query-gic-capability command unconditionallyDaniel P. Berrangé1-1/+1
This removes the TARGET_ARM condition from the query-gic-capability command. This requires providing a QMP command stub for non-ARM targets. This in turn requires moving the command out of misc-target.json, since that will trigger symbol poisoning errors when built from target independent code. Following the earlier precedent, this creates a misc-arm.json file to hold this ARM specific command. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-5-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: make SEV commands unconditionally availableDaniel P. Berrangé2-33/+1
This removes the TARGET_I386 condition from the SEV confidential virtualization commands, moving them to the recently introduced misc-i386.json QAPI file, given they are inherantly i386 specific commands. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-4-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28target/sparc: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+13
Check address masking state for sparc64. Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/s390x: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+9
Use the existing wrap_address function. Cc: qemu-s390x@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/riscv: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+26
Check 32 vs 64-bit and pointer masking state. Cc: qemu-riscv@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/ppc: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+7
Check 32 vs 64-bit state. Cc: qemu-ppc@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/mips: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+9
Check 32 vs 64-bit addressing state. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/loongarch: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+7
Check va32 state. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/i386: Fill in TCGCPUOps.pointer_wrapRichard Henderson1-0/+7
Check 32 vs 64-bit state. Cc: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/arm: Fill in TCGCPUOps.pointer_wrapRichard Henderson2-0/+25
For a-profile, check A32 vs A64 state. For m-profile, use cpu_pointer_wrap_uint32. Cc: qemu-arm@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target: Use cpu_pointer_wrap_uint32 for 32-bit targetsRichard Henderson7-0/+12
M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are all 32-bit targets. AVR is more complicated, but using a 32-bit wrap preserves current behaviour. Cc: Michael Rolnik <mrolnik@gmail.com> Cc: Laurent Vivier <laurent@vivier.eu> Cc: Stafford Horne <shorne@gmail.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Max Filippov <jcmvbkbc@gmail.com> Tested-by Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore) Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target: Use cpu_pointer_wrap_notreached for strict align targetsRichard Henderson3-0/+3
Alpha, HPPA, and SH4 always use aligned addresses, and therefore never produce accesses that cross pages. Cc: Helge Deller <deller@gmx.de> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/sh4: Use MO_ALIGN for system UNALIGN()Richard Henderson1-1/+1
This should have been done before removing TARGET_ALIGNED_ONLY, as we did for hppa and alpha. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Fixes: 8244189419f9 ("target/sh4: Remove TARGET_ALIGNED_ONLY") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Simplify compute_ldst_addr_type{a,b}Richard Henderson1-13/+13
Require TCGv_i32 and TCGv be identical, so drop the extensions. Return constants when possible instead of a mov into a temporary. Return register inputs unchanged when possible. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Drop DisasContext.r0Richard Henderson1-22/+2
Return a constant 0 from reg_for_read, and a new temporary from reg_for_write. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Fix printf format in mmu_translateRichard Henderson1-1/+2
Use TARGET_FMT_lx to match the target_ulong type of vaddr. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Use TCGv_i64 for compute_ldst_addr_eaRichard Henderson1-12/+12
Use an explicit 64-bit type for extended addresses. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Use uint64_t for CPUMBState.earRichard Henderson2-2/+2
Use an explicit 64-bit type for EAR. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Implement extended address load/store out of lineRichard Henderson3-12/+90
Use helpers and address_space_ld/st instead of inline loads and stores. This allows us to perform operations on physical addresses wider than virtual addresses. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Split out mb_transaction_failed_internalRichard Henderson1-28/+42
Use an explicit 64-bit type for the address to store in EAR. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Introduce helper_unaligned_accessRichard Henderson2-6/+13
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28target/microblaze: Split out mb_unaligned_access_internalRichard Henderson1-28/+36
Use an explicit 64-bit type for the address to store in EAR. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-27target/sparc: don't set FSR_NVA when comparing unordered floatsClément Chigot1-1/+0
FSR_NVA should be set when one of the operands is a signaling NaN or when using FCMPEx instructions. But those cases are already handled within check_ieee_exception or floatxx_compare functions. Otherwise, it should be left untouched. FTR, this was detected by inf-compare-[5678] tests within gcc testsuites. Signed-off-by: Clément Chigot <chigot@adacore.com> Message-Id: <20250425093513.863289-1-chigot@adacore.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2025-05-27target/i386/emulate: more lflags cleanupsPaolo Bonzini1-8/+8
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-26target/arm: remove explicit dependencies listedPierrick Bouvier1-1/+1
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20250521223414.248276-4-pierrick.bouvier@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-22Merge tag 'hppa-fpe-fixup-pull-request' of ↵Stefan Hajnoczi2-3/+21
https://github.com/hdeller/qemu-hppa into staging HPPA floating point exception handling fixes Fixes and improvements in the floating point exception handling in the hppa system and user emulation. # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCaC7b/QAKCRD3ErUQojoP # X8IPAQCZGjG3+iwJJuJkL6dSu7WKWgidX16zIxeRYQl+FXTpkAD9FBQ/nDP+EAFN # 5hQTeiixyj3xIsZHPeHwfzhWiBUwQAo= # =Q3zi # -----END PGP SIGNATURE----- # gpg: Signature made Thu 22 May 2025 04:10:37 EDT # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'hppa-fpe-fixup-pull-request' of https://github.com/hdeller/qemu-hppa: target/hppa: Fix FPE exceptions linux-user/hppa: Send proper si_code on SIGFPE exception target/hppa: Copy instruction code into fr1 on FPU assist fault Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-20target/riscv: remove .instance_post_initPaolo Bonzini1-6/+2
Unlike other uses of .instance_post_init, accel_cpu_instance_init() *registers* properties, and therefore must be run before device_post_init() which sets them to their values from -global. In order to move all registration of properties to .instance_init, call accel_cpu_instance_init() at the end of riscv_cpu_init(). Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: convert Xiangshan Nanhu to RISCVCPUDefPaolo Bonzini1-57/+23
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: convert Ventana V1 to RISCVCPUDefPaolo Bonzini1-40/+35
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: convert TT Ascalon to RISCVCPUDefPaolo Bonzini1-67/+60
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: convert THead C906 to RISCVCPUDefPaolo Bonzini1-33/+28
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: generalize custom CSR functionalityPaolo Bonzini4-23/+40
While at it, constify it so that the RISCVCSR array in RISCVCPUDef can also be const. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: th: make CSR insertion test a bit more intuitivePaolo Bonzini1-9/+4
In preparation for generalizing the custom CSR functionality, make the test return bool instead of int. Make the insertion_test optional, too. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: convert SiFive U models to RISCVCPUDefPaolo Bonzini2-43/+37
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: convert ibex CPU models to RISCVCPUDefPaolo Bonzini1-23/+16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: convert SiFive E CPU models to RISCVCPUDefPaolo Bonzini2-54/+21
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: convert dynamic CPU models to RISCVCPUDefPaolo Bonzini1-82/+31
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: convert bare CPU models to RISCVCPUDefPaolo Bonzini1-41/+17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: convert profile CPU models to RISCVCPUDefPaolo Bonzini2-38/+48
Profile CPUs reuse the instance_init function for bare CPUs; make them proper subclasses instead. Enabling a profile is now done based on the RISCVCPUDef struct: even though there is room for only one in RISCVCPUDef, subclasses check that the parent class's profile is enabled through the parent profile mechanism. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: convert abstract CPU classes to RISCVCPUDefPaolo Bonzini2-48/+46
Start from the top of the hierarchy: dynamic and vendor CPUs are just markers, whereas bare CPUs can have their instance_init function replaced by RISCVCPUDef. The only difference is that the maximum supported SATP mode has to be specified separately for 32-bit and 64-bit modes. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: add more RISCVCPUDef fieldsPaolo Bonzini3-1/+51
Allow using RISCVCPUDef to replicate all the logic of custom .instance_init functions. To simulate inheritance, merge the child's RISCVCPUDef with the parent and then finally move it to the CPUState at the end of TYPE_RISCV_CPU's own instance_init function. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: include default value in cpu_cfg_fields.h.incPaolo Bonzini2-12/+12
In preparation for adding a function to merge two RISCVCPUConfigs (pulling values from the parent if they are not overridden) annotate cpu_cfg_fields.h.inc with the default value of the fields. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: move RISCVCPUConfig fields to a header filePaolo Bonzini2-160/+173
To support merging a subclass's RISCVCPUDef into the superclass, a list of all the CPU features is needed. Put them into a header file that can be included multiple times, expanding the macros BOOL_FIELD and TYPE_FIELD to different operations. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: merge riscv_cpu_class_init with the class_base functionPaolo Bonzini1-11/+10
Since all TYPE_RISCV_CPU subclasses support a class_data of type RISCVCPUDef, process it even before calling the .class_init function for the subclasses. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: store RISCVCPUDef struct directly in the classPaolo Bonzini7-28/+38
Prepare for adding more fields to RISCVCPUDef and reading them in riscv_cpu_init: instead of storing the misa_mxl_max field in RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct and go through it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: introduce RISCVCPUDefPaolo Bonzini2-9/+22
Start putting all the CPU definitions in a struct. Later this will replace instance_init functions with declarative code, for now just remove the ugly cast of class_data. Reviewed-by: Alistair Francis <alistair23@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: move satp_mode.{map,init} out of CPUConfigPaolo Bonzini3-30/+30
They are used to provide the nice QOM properties for svNN, but the canonical source of the CPU configuration is now cpu->cfg.max_satp_mode. Store them in the ArchCPU struct. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: remove supported from RISCVSATPMapPaolo Bonzini2-11/+23
"supported" can be computed on the fly based on the max_satp_mode. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: update max_satp_mode based on QOM propertiesPaolo Bonzini3-20/+17
Almost all users of cpu->cfg.satp_mode care about the "max" value satp_mode_max_from_map(cpu->cfg.satp_mode.map). Convert the QOM properties back into it. For TCG, deduce the bitmap of supported modes from valid_vm[]. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20target/riscv: cpu: store max SATP mode as a single integerPaolo Bonzini3-7/+8
The maximum available SATP mode implies all the shorter virtual address sizes. Store it in RISCVCPUConfig and avoid recomputing it via satp_mode_max_from_map. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2025-09-19 23:16:41 +0000