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2023-05-18Hexagon (target/hexagon) Short-circuit more HVX single instruction packetsTaylor Simpson4-2/+44
The generated helpers for HVX use pass-by-reference, so they can't short-circuit when the reads/writes overlap. The instructions with overrides are OK because they use tcg_gen_gvec_*. We add a flag has_hvx_helper to DisasContext and extend gen_analyze_funcs to set the flag when the instruction is an HVX instruction with a generated helper. We add an override for V6_vcombine so that it can be short-circuited along with a test case in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-15-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Short-circuit packet HVX writesTaylor Simpson2-2/+50
In certain cases, we can avoid the overhead of writing to future_VRegs and write directly to VRegs. We consider HVX reads/writes when computing ctx->need_commit. Then, we can early-exit from gen_commit_hvx. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-14-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Short-circuit packet predicate writesTaylor Simpson3-6/+24
In certain cases, we can avoid the overhead of writing to hex_new_pred_value and write directly to hex_pred. We consider predicate reads/writes when computing ctx->need_commit. The get_result_pred() function uses this field to decide between hex_new_pred_value and hex_pred. Then, we can early-exit from gen_pred_writes. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-13-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Short-circuit packet register writesTaylor Simpson16-30/+128
In certain cases, we can avoid the overhead of writing to hex_new_value and write directly to hex_gpr. We add need_commit field to DisasContext indicating if the end-of-packet commit is needed. If it is not needed, get_result_gpr() and get_result_gpr_pair() can return hex_gpr. We pass the ctx->need_commit to helpers when needed. Finally, we can early-exit from gen_reg_writes during packet commit. There are a few instructions whose semantics write to the result before reading all the inputs. Therefore, the idef-parser generated code is incompatible with short-circuit. We tell idef-parser to skip them. For debugging purposes, we add a cpu property to turn off short-circuit. When the short-circuit property is false, we skip the analysis and force the end-of-packet commit. Here's a simple example of the TCG generated for 0x004000b4: 0x7800c020 { R0 = #0x1 } BEFORE: ---- 004000b4 movi_i32 new_r0,$0x1 mov_i32 r0,new_r0 AFTER: ---- 004000b4 movi_i32 r0,$0x1 This patch reintroduces a use of check_for_attrib, so we remove the G_GNUC_UNUSED added earlier in this series. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20230427230012.3800327-12-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Mark registers as read during packet analysisTaylor Simpson5-15/+97
Have gen_analyze_funcs mark the registers that are read by the instruction. We also mark the implicit reads using instruction attributes. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-11-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Don't overlap dest writes with source readsTaylor Simpson1-16/+29
When generating TCG, make sure we have read all the operand registers before writing to the destination registers. This is a prerequesite for short-circuiting where the source and dest operands could be the same. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-10-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Clean up pred_written usageTaylor Simpson2-46/+23
Only endloop instructions will conditionally write to a predicate. When there is an endloop instruction, we preload the values into new_pred_value. The only place pred_written is needed is when HEX_DEBUG is on. We remove the last use of check_for_attrib. However, new uses will be introduced later in this series, so we mark it with G_GNUC_UNUSED. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-9-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Eliminate uses of log_pred_write functionTaylor Simpson5-19/+104
These instructions have implicit writes to registers, so we don't want them to be helpers when idef-parser is off. The following instructions are overriden S2_cabacdecbin SA1_cmpeqi Remove the log_pred_write function from op_helper.c Remove references in macros.h Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-8-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Remove log_reg_write from op_helper.[ch]Taylor Simpson3-35/+0
With the overrides added in prior commits, this function is not used Remove references in macros.h Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-7-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add overrides for clr[tf]newTaylor Simpson2-4/+16
These instructions have implicit reads from p0, so we don't want them in helpers when idef-parser is off. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-6-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add overrides for allocframe/deallocframeTaylor Simpson2-0/+79
These instructions have implicit writes to registers, so we don't want them to be helpers when idef-parser is off. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-5-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add overrides for loop setup instructionsTaylor Simpson2-0/+65
These instructions have implicit writes to registers, so we don't want them to be helpers when idef-parser is off. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-4-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_writeTaylor Simpson6-12/+14
Add DisasContext arg to gen_log_reg_write_pair also Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-3-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add v73 scalar instructionsTaylor Simpson4-1/+13
The following instructions are added J2_callrh J2_junprh Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-9-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add v69 HVX instructionsTaylor Simpson4-0/+68
The following instructions are added V6_vasrvuhubrndsat V6_vasrvuhubsat V6_vasrvwuhrndsat V6_vasrvwuhsat V6_vassign_tmp V6_vcombine_tmp V6_vmpyuhvs Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-7-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add v68 HVX instructionsTaylor Simpson3-3/+295
The following instructions are added V6_v6mpyvubs10_vxx V6_v6mpyhubs10_vxx V6_v6mpyvubs10 V6_v6mpyhubs10 Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-5-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add v68 scalar instructionsTaylor Simpson6-6/+63
The following instructions are added L2_loadw_aq L4_loadd_aq R6_release_at_vi R6_release_st_vi S2_storew_rl_at_vi S4_stored_rl_at_vi S2_storew_rl_st_vi S4_stored_rl_st_vi The release instructions are nop's in qemu. The others behave as loads/stores. The encodings for these instructions changed some "don't care" bits L2_loadw_locked L4_loadd_locked S2_storew_locked S4_stored_locked Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-3-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add support for v68/v69/v71/v73Taylor Simpson3-8/+18
Add support for the ELF flags Move target/hexagon/cpu.[ch] to be v73 Change the compiler flag used by "make check-tcg" The decbin instruction is removed in Hexagon v73, so check the version before trying to compile the instruction. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-2-tsimpson@quicinc.com>
2023-05-11target/loongarch: Do not include tcg-ldst.hRichard Henderson2-2/+0
This header is supposed to be private to tcg and in fact does not need to be included here at all. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11target/sh4: Use MO_ALIGN where requiredRichard Henderson1-36/+66
Mark all memory operations that are not already marked with UNALIGN. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11target/nios2: Remove TARGET_ALIGNED_ONLYRichard Henderson1-0/+10
In gen_ldx/gen_stx, the only two locations for memory operations, mark the operation as either aligned (softmmu) or unaligned (user-only, as if emulated by the kernel). Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11target/mips: Use MO_ALIGN instead of 0Richard Henderson1-1/+1
The opposite of MO_UNALN is MO_ALIGN. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11target/mips: Add missing default_tcg_memop_maskRichard Henderson4-28/+42
Memory operations that are not already aligned, or otherwise marked up, require addition of ctx->default_tcg_memop_mask. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11target/mips: Add MO_ALIGN to gen_llwp, gen_scwpRichard Henderson1-2/+3
These are atomic operations, so mark as requiring alignment. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11target/m68k: Fix gen_load_fp for OS_LONGRichard Henderson1-0/+1
Case was accidentally dropped in b7a94da9550b. Tested-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-10target/loongarch: Terminate vmstate subsections listRichard Henderson1-0/+1
This list requires a NULL terminator. Fixes: 16f5396cec23 ("target/loongarch: Add LSX data type VReg") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230510062405.127260-1-richard.henderson@linaro.org>
2023-05-08target/i386: Add EPYC-Genoa model to support Zen 4 processor seriesBabu Moger1-0/+122
Adds the support for AMD EPYC Genoa generation processors. The model display for the new processor will be EPYC-Genoa. Adds the following new feature bits on top of the feature bits from the previous generation EPYC models. avx512f : AVX-512 Foundation instruction avx512dq : AVX-512 Doubleword & Quadword Instruction avx512ifma : AVX-512 Integer Fused Multiply Add instruction avx512cd : AVX-512 Conflict Detection instruction avx512bw : AVX-512 Byte and Word Instructions avx512vl : AVX-512 Vector Length Extension Instructions avx512vbmi : AVX-512 Vector Byte Manipulation Instruction avx512_vbmi2 : AVX-512 Additional Vector Byte Manipulation Instruction gfni : AVX-512 Galois Field New Instructions avx512_vnni : AVX-512 Vector Neural Network Instructions avx512_bitalg : AVX-512 Bit Algorithms, add bit algorithms Instructions avx512_vpopcntdq: AVX-512 AVX-512 Vector Population Count Doubleword and Quadword Instructions avx512_bf16 : AVX-512 BFLOAT16 instructions la57 : 57-bit virtual address support (5-level Page Tables) vnmi : Virtual NMI (VNMI) allows the hypervisor to inject the NMI into the guest without using Event Injection mechanism meaning not required to track the guest NMI and intercepting the IRET. auto-ibrs : The AMD Zen4 core supports a new feature called Automatic IBRS. It is a "set-and-forget" feature that means that, unlike e.g., s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation resources automatically across CPL transitions. Signed-off-by: Babu Moger <babu.moger@amd.com> Message-Id: <20230504205313.225073-8-babu.moger@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-08target/i386: Add VNMI and automatic IBRS feature bitsBabu Moger2-2/+5
Add the following featute bits. vnmi: Virtual NMI (VNMI) allows the hypervisor to inject the NMI into the guest without using Event Injection mechanism meaning not required to track the guest NMI and intercepting the IRET. The presence of this feature is indicated via the CPUID function 0x8000000A_EDX[25]. automatic-ibrs : The AMD Zen4 core supports a new feature called Automatic IBRS. It is a "set-and-forget" feature that means that, unlike e.g., s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation resources automatically across CPL transitions. The presence of this feature is indicated via the CPUID function 0x80000021_EAX[8]. The documention for the features are available in the links below. a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision 40332 4.05 Date October 2022 Signed-off-by: Santosh Shukla <santosh.shukla@amd.com> Signed-off-by: Kim Phillips <kim.phillips@amd.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf Message-Id: <20230504205313.225073-7-babu.moger@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-08target/i386: Add missing feature bits in EPYC-Milan modelBabu Moger1-0/+70
Add the following feature bits for EPYC-Milan model and bump the version. vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support vpclmulqdq : Vector VPCLMULQDQ instruction support stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced performance and may be left Always on amd-psfd : Predictive Store Forward Disable no-nested-data-bp : Processor ignores nested data breakpoints lfence-always-serializing : LFENCE instruction is always serializing null-sel-clr-base : Null Selector Clears Base. When this bit is set, a null segment load clears the segment base These new features will be added in EPYC-Milan-v2. The "-cpu help" output after the change will be. x86 EPYC-Milan (alias configured by machine type) x86 EPYC-Milan-v1 AMD EPYC-Milan Processor x86 EPYC-Milan-v2 AMD EPYC-Milan Processor The documentation for the features are available in the links below. a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING c. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision 40332 4.05 Date October 2022 Signed-off-by: Babu Moger <babu.moger@amd.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf Message-Id: <20230504205313.225073-6-babu.moger@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-08target/i386: Add feature bits for CPUID_Fn80000021_EAXBabu Moger2-0/+32
Add the following feature bits. no-nested-data-bp : Processor ignores nested data breakpoints. lfence-always-serializing : LFENCE instruction is always serializing. null-sel-cls-base : Null Selector Clears Base. When this bit is set, a null segment load clears the segment base. The documentation for the features are available in the links below. a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision 40332 4.05 Date October 2022 Signed-off-by: Babu Moger <babu.moger@amd.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf Message-Id: <20230504205313.225073-5-babu.moger@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-08target/i386: Add a couple of feature bits in 8000_0008_EBXBabu Moger2-2/+6
Add the following feature bits. amd-psfd : Predictive Store Forwarding Disable: PSF is a hardware-based micro-architectural optimization designed to improve the performance of code execution by predicting address dependencies between loads and stores. While SSBD (Speculative Store Bypass Disable) disables both PSF and speculative store bypass, PSFD only disables PSF. PSFD may be desirable for the software which is concerned with the speculative behavior of PSF but desires a smaller performance impact than setting SSBD. Depends on the following kernel commit: b73a54321ad8 ("KVM: x86: Expose Predictive Store Forwarding Disable") stibp-always-on : Single Thread Indirect Branch Prediction mode has enhanced performance and may be left always on. The documentation for the features are available in the links below. a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING Signed-off-by: Babu Moger <babu.moger@amd.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Message-Id: <20230504205313.225073-4-babu.moger@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-08target/i386: Add new EPYC CPU versions with updated cache_infoMichael Roth1-0/+118
Introduce new EPYC cpu versions: EPYC-v4 and EPYC-Rome-v3. The only difference vs. older models is an updated cache_info with the 'complex_indexing' bit unset, since this bit is not currently defined for AMD and may cause problems should it be used for something else in the future. Setting this bit will also cause CPUID validation failures when running SEV-SNP guests. Signed-off-by: Michael Roth <michael.roth@amd.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20230504205313.225073-3-babu.moger@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-08target/i386: allow versioned CPUs to specify new cache_infoMichael Roth1-3/+32
New EPYC CPUs versions require small changes to their cache_info's. Because current QEMU x86 CPU definition does not support versioned cach_info, we would have to declare a new CPU type for each such case. To avoid the dup work, add "cache_info" in X86CPUVersionDefinition", to allow new cache_info pointers to be specified for a new CPU version. Co-developed-by: Wei Huang <wei.huang2@amd.com> Signed-off-by: Wei Huang <wei.huang2@amd.com> Signed-off-by: Michael Roth <michael.roth@amd.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20230504205313.225073-2-babu.moger@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-06Merge tag 'pull-loongarch-20230506' of https://gitlab.com/gaosong/qemu into ↵Richard Henderson18-55/+9986
staging Add LoongArch LSX instructions. # -----BEGIN PGP SIGNATURE----- # # iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZFXxGwAKCRBAov/yOSY+ # 39EoA/0Uy2DPz6g7J5+9tcIRk9jLrp36aYQJ9J8zRJd226YFvHSfiBWSIteMFOEX # Z0Jx1bL6N97KK/HA74Nx++x0kVuplEGp1s5cO/odL3gYy8RaJm23p9iaDa0D/UaB # ygLvXtuzN4unDFP5EF/wa9zRkDb7qX2iBBvc8OIal7eT4dDX+g== # =gyVU # -----END PGP SIGNATURE----- # gpg: Signature made Sat 06 May 2023 07:18:03 AM BST # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20230506' of https://gitlab.com/gaosong/qemu: (45 commits) hw/intc: don't use target_ulong for LoongArch ipi target/loongarch: CPUCFG support LSX target/loongarch: Use {set/get}_gpr replace to cpu_fpr target/loongarch: Implement vldi target/loongarch: Implement vld vst target/loongarch: Implement vilvl vilvh vextrins vshuf target/loongarch: Implement vreplve vpack vpick target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr target/loongarch: Implement vbitsel vset target/loongarch: Implement vfcmp target/loongarch: Implement vseq vsle vslt target/loongarch: Implement LSX fpu fcvt instructions target/loongarch: Implement LSX fpu arith instructions target/loongarch: Implement vfrstp target/loongarch: Implement vbitclr vbitset vbitrev target/loongarch: Implement vpcnt target/loongarch: Implement vclo vclz target/loongarch: Implement vssrlrn vssrarn target/loongarch: Implement vssrln vssran target/loongarch: Implement vsrlrn vsrarn ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-06target/loongarch: CPUCFG support LSXSong Gao1-0/+1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-45-gaosong@loongson.cn>
2023-05-06target/loongarch: Use {set/get}_gpr replace to cpu_fprSong Gao5-43/+129
Introduce set_fpr() and get_fpr() and remove cpu_fpr. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-44-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement vldiSong Gao3-0/+148
This patch includes: - VLDI. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-43-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement vld vstSong Gao4-0/+239
This patch includes: - VLD[X], VST[X]; - VLDREPL.{B/H/W/D}; - VSTELM.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-42-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement vilvl vilvh vextrins vshufSong Gao5-0/+248
This patch includes: - VILV{L/H}.{B/H/W/D}; - VSHUF.{B/H/W/D}; - VSHUF4I.{B/H/W/D}; - VPERMI.W; - VEXTRINS.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-41-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement vreplve vpack vpickSong Gao5-0/+319
This patch includes: - VREPLVE[I].{B/H/W/D}; - VBSLL.V, VBSRL.V; - VPACK{EV/OD}.{B/H/W/D}; - VPICK{EV/OD}.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-40-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vrSong Gao3-0/+173
This patch includes: - VINSGR2VR.{B/H/W/D}; - VPICKVE2GR.{B/H/W/D}[U]; - VREPLGR2VR.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-39-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement vbitsel vsetSong Gao5-0/+174
This patch includes: - VBITSEL.V; - VBITSELI.B; - VSET{EQZ/NEZ}.V; - VSETANYEQZ.{B/H/W/D}; - VSETALLNEZ.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-38-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement vfcmpSong Gao5-0/+190
This patch includes: - VFCMP.cond.{S/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-37-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement vseq vsle vsltSong Gao5-0/+332
This patch includes: - VSEQ[I].{B/H/W/D}; - VSLE[I].{B/H/W/D}[U]; - VSLT[I].{B/H/W/D/}[U]. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-36-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement LSX fpu fcvt instructionsSong Gao5-0/+600
This patch includes: - VFCVT{L/H}.{S.H/D.S}; - VFCVT.{H.S/S.D}; - VFRINT[{RNE/RZ/RP/RM}].{S/D}; - VFTINT[{RNE/RZ/RP/RM}].{W.S/L.D}; - VFTINT[RZ].{WU.S/LU.D}; - VFTINT[{RNE/RZ/RP/RM}].W.D; - VFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S; - VFFINT.{S.W/D.L}[U]; - VFFINT.S.L, VFFINT{L/H}.D.W. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-35-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement LSX fpu arith instructionsSong Gao8-1/+377
This patch includes: - VF{ADD/SUB/MUL/DIV}.{S/D}; - VF{MADD/MSUB/NMADD/NMSUB}.{S/D}; - VF{MAX/MIN}.{S/D}; - VF{MAXA/MINA}.{S/D}; - VFLOGB.{S/D}; - VFCLASS.{S/D}; - VF{SQRT/RECIP/RSQRT}.{S/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-34-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement vfrstpSong Gao5-0/+61
This patch includes: - VFRSTP[I].{B/H}. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-33-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement vbitclr vbitset vbitrevSong Gao5-0/+437
This patch includes: - VBITCLR[I].{B/H/W/D}; - VBITSET[I].{B/H/W/D}; - VBITREV[I].{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-32-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement vpcntSong Gao5-0/+38
This patch includes: - VPCNT.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-31-gaosong@loongson.cn>
2023-05-06target/loongarch: Implement vclo vclzSong Gao5-0/+67
This patch includes: - VCLO.{B/H/W/D}; - VCLZ.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-30-gaosong@loongson.cn>
generated by cgit v1.1 at 2025-01-04 10:05:35 +0000