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2020-10-29Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.2-20201028' into...Peter Maydell10-22/+24
2020-10-29Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201027-...Peter Maydell2-2/+7
2020-10-28Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' in...Peter Maydell6-10/+14
2020-10-28Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-re...Peter Maydell1-0/+1
2020-10-28ppc/: fix some comment spelling errorszhaolichang9-14/+14
2020-10-28target/ppc: Fix kvmppc_load_htab_chunk() error reportingGreg Kurz2-8/+8
2020-10-28spapr: Unrealize vCPUs with qdev_unrealize()Greg Kurz1-0/+2
2020-10-27linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTIRichard Henderson2-2/+7
2020-10-27target/rx: Fix Lesser GPL version numberChetan Pant1-1/+1
2020-10-27target/rx: Fix some comment spelling errorsLichang Zhao2-2/+2
2020-10-27target/sh4: fix some comment spelling errorsLichang Zhao3-3/+3
2020-10-27target/sh4: Update coding style to make checkpatch.pl happyPhilippe Mathieu-Daudé2-6/+10
2020-10-26Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20201026' into stagingPeter Maydell4-2/+14
2020-10-26target/xtensa: enable all coprocessors for linux-userMax Filippov1-0/+1
2020-10-22target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang2-12/+34
2020-10-22target/riscv: Fix implementation of HLVX.WU instructionGeorg Kotheimer1-3/+3
2020-10-22target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interruptGeorg Kotheimer1-1/+3
2020-10-22target/riscv: Fix update of hstatus.SPVPGeorg Kotheimer1-1/+1
2020-10-22riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis2-2/+7
2020-10-22s390x: pv: Fix diag318 PV fencingJanosch Frank4-2/+14
2020-10-20target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extensionPeter Maydell3-0/+16
2020-10-20target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16Peter Maydell1-19/+28
2020-10-20target/arm: Fix has_vfp/has_neon ID reg squashing for M-profilePeter Maydell1-12/+19
2020-10-20target/arm: Implement v8.1M low-overhead-loop instructionsPeter Maydell2-2/+99
2020-10-20target/arm: Implement v8.1M branch-future insns (as NOPs)Peter Maydell3-1/+38
2020-10-20target/arm: Don't allow BLX imm for M-profilePeter Maydell1-0/+8
2020-10-20target/arm: Make the t32 insn[25:23]=111 group non-overlappingPeter Maydell1-13/+11
2020-10-20target/arm: Implement v8.1M conditional-select insnsPeter Maydell2-0/+63
2020-10-20target/arm: Implement v8.1M NOCP handlingPeter Maydell3-6/+22
2020-10-20target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11Richard Henderson2-8/+10
2020-10-20target/arm: Fix reported EL for mte_check_failRichard Henderson1-7/+3
2020-10-20target/arm: Remove redundant mmu_idx lookupRichard Henderson1-2/+1
2020-10-20target/arm: Use tlb_flush_page_bits_by_mmuidx*Richard Henderson1-7/+39
2020-10-20target/arm: AArch32 VCVT fixed-point to float is always round-to-nearestPeter Maydell3-13/+47
2020-10-20target/arm: Fix SMLAD incorrect setting of Q bitPeter Maydell1-11/+49
2020-10-19Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-next-20201017' ...Peter Maydell9-109/+756
2020-10-17Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell1-0/+1
2020-10-17hax: unbreak accelerator cpu code after cpus.c splitClaudio Fontana1-0/+1
2020-10-17target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)Philippe Mathieu-Daudé1-1/+1
2020-10-17target/mips/cpu: Display warning when CPU is used without input clockPhilippe Mathieu-Daudé1-0/+10
2020-10-17target/mips/cpu: Introduce mips_cpu_create_with_clock() helperPhilippe Mathieu-Daudé2-0/+24
2020-10-17target/mips/cpu: Allow the CPU to use dynamic frequenciesPhilippe Mathieu-Daudé2-2/+13
2020-10-17target/mips/cpu: Make cp0_count_rate a propertyPhilippe Mathieu-Daudé2-8/+20
2020-10-17target/mips/cpu: Calculate the CP0 timer period using the CPU frequencyPhilippe Mathieu-Daudé1-2/+2
2020-10-17target/mips: Move cp0_count_ns to CPUMIPSStatePhilippe Mathieu-Daudé3-17/+28
2020-10-17target/mips/cp0_timer: Document TIMER_PERIOD originPhilippe Mathieu-Daudé1-1/+11
2020-10-17target/mips/cp0_timer: Explicit unit in variable namePhilippe Mathieu-Daudé1-9/+10
2020-10-17target/mips: Move cpu_mips_get_random() with CP0 helpersPhilippe Mathieu-Daudé3-26/+26
2020-10-17target/mips/op_helper: Log unimplemented cache opcodePhilippe Mathieu-Daudé1-0/+9
2020-10-17target/mips/op_helper: Document Invalidate/Writeback opcodes as no-opPhilippe Mathieu-Daudé1-0/+5