aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Collapse)AuthorFilesLines
2020-10-13i386: Register most CPU properties as class propertiesEduardo Habkost1-32/+34
Class properties make QOM introspection simpler and easier, as they don't require an object to be instantiated. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20200921221045.699690-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-10-13target/sparc/int32_helper: Remove duplicated 'Tag Overflow' entryPhilippe Mathieu-Daudé1-1/+0
Commit 0b09be2b2f ("Nicer debug output for exceptions") added twice the same "Tag Overflow" entry, remove the extra one. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20201011200112.3222822-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-10-12target/i386/cpu: Update comment that mentions TexinfoMarkus Armbruster1-1/+2
Missed in commit 41fba1618b "docs/system: convert the documentation of deprecated features to rST." Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200929075824.1517969-3-armbru@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-10-09ppc: Fix return value in cpu_post_load() error pathGreg Kurz1-4/+5
VMState handlers are supposed to return negative errno values on failure. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <20200914123505.612812-4-groug@kaod.org> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-09ppc: Add a return value to ppc_set_compat() and ppc_set_compat_all()Greg Kurz2-13/+17
As recommended in "qapi/error.h", indicate success / failure with a return value. Since ppc_set_compat() is called from a VMState handler, let's make it an int so that it propagates any negative errno returned by kvmppc_set_compat(). Do the same for ppc_set_compat_all() for consistency, even if it isn't called in a context where a negative errno is required on failure. This will allow to simplify error handling in the callers. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <20200914123505.612812-3-groug@kaod.org> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-08target/arm: Make '-cpu max' have a 48-bit PAPeter Maydell1-0/+4
QEMU supports a 48-bit physical address range, but we don't currently expose it in the '-cpu max' ID registers (you get the same range as Cortex-A57, which is 44 bits). Set the ID_AA64MMFR0.PARange field to indicate 48 bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201001160116.18095-1-peter.maydell@linaro.org
2020-10-08hw/arm/virt: Implement kvm-steal-timeAndrew Jones6-6/+131
We add the kvm-steal-time CPU property and implement it for machvirt. A tiny bit of refactoring was also done to allow pmu and pvtime to use the same vcpu device helper functions. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20201001061718.101915-7-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-08target/arm/kvm: Make uncalled stubs explicitly unreachableAndrew Jones1-19/+32
When we compile without KVM support !defined(CONFIG_KVM) we generate stubs for functions that the linker will still encounter. Sometimes these stubs can be executed safely and are placed in paths where they get executed with or without KVM. Other functions should never be called without KVM. Those functions should be guarded by kvm_enabled(), but should also be robust to refactoring mistakes. Putting a g_assert_not_reached() in the function should help. Additionally, the g_assert_not_reached() calls may actually help the linker remove some code. We remove the stubs for kvm_arm_get/put_virtual_time(), as they aren't necessary at all - the only caller is in kvm.c Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20201001061718.101915-3-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-05hax: remove hax specific functions from global includesClaudio Fontana7-6/+21
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-05whpx: remove whpx specific functions from global includesClaudio Fontana1-0/+17
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-05hvf: remove hvf specific functions from global includesClaudio Fontana3-1/+10
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-05cpus: add handle_interrupt to the CpusAccel interfaceClaudio Fontana3-29/+0
kvm: uses the generic handler qtest: uses the generic handler whpx: changed to use the generic handler (identical implementation) hax: changed to use the generic handler (identical implementation) hvf: changed to use the generic handler (identical implementation) tcg: adapt tcg-cpus to point to the tcg-specific handler Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-05cpus: extract out hvf-specific code to target/i386/hvf/Claudio Fontana4-0/+152
register a "CpusAccel" interface for HVF as well. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> [added const] Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-05cpus: extract out whpx-specific code to target/i386/Claudio Fontana4-1/+120
register a "CpusAccel" interface for WHPX as well. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-05cpus: extract out hax-specific code to target/i386/Claudio Fontana7-3/+148
register a "CpusAccel" interface for HAX as well. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-05icount: rename functions to be consistent with the module nameClaudio Fontana2-4/+4
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-05cpu-timers, icount: new modulesClaudio Fontana3-4/+6
refactoring of cpus.c continues with cpu timer state extraction. cpu-timers: responsible for the softmmu cpu timers state, including cpu clocks and ticks. icount: counts the TCG instructions executed. As such it is specific to the TCG accelerator. Therefore, it is built only under CONFIG_TCG. One complication is due to qtest, which uses an icount field to warp time as part of qtest (qtest_clock_warp). In order to solve this problem, provide a separate counter for qtest. This requires fixing assumptions scattered in the code that qtest_enabled() implies icount_enabled(), checking each specific case. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [remove redundant initialization with qemu_spice_init] Reviewed-by: Alex Bennée <alex.bennee@linaro.org> [fix lingering calls to icount_get] Signed-off-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-05Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell2-11/+49
staging * move target configuration to default-configs/targets (myself) * Memory failure event (Zhenwei) # gpg: Signature made Mon 05 Oct 2020 08:14:29 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: dockerfiles: add diffutils to Fedora tests: tcg: do not use implicit rules target-i386: post memory failure event to QMP qapi/run-state.json: introduce memory failure event target-i386: seperate MCIP & MCE_MASK error reason meson: move sparse detection to Meson and rewrite check_sparse.py default-configs: remove redundant keys default-configs: use TARGET_ARCH key configure: move OpenBSD W^X test to meson default-configs: remove default-configs/devices for user-mode targets configure: remove target configuration configure: remove useless config-target.mak symbols configure: compute derivatives of target name in meson configure: remove dead variable configure: move accelerator logic to meson configure: rewrite accelerator defaults as tests configure: convert accelerator variables to meson options default-configs: move files to default-configs/devices/ travis: remove TCI test Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # configure
2020-10-04target-i386: post memory failure event to QMPzhenwei pi2-5/+32
Post memory failure event through QMP to handle hardware memory corrupted event. Rather than simply printing to the log, QEMU could report more effective message to the client. For example, if a guest receives an MCE, evacuating the host could be a good idea. Signed-off-by: zhenwei pi <pizhenwei@bytedance.com> Message-Id: <20200930100440.1060708-4-pizhenwei@bytedance.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-04target-i386: seperate MCIP & MCE_MASK error reasonzhenwei pi1-7/+18
Previously we would only get a simple string "Triple fault" in qemu log. Add detailed message for the two reasons to describe why qemu has to reset the guest. Signed-off-by: zhenwei pi <pizhenwei@bytedance.com> Message-Id: <20200930100440.1060708-2-pizhenwei@bytedance.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-03disas: Enable capstone disassembly for s390xRichard Henderson1-0/+4
Enable s390x, aka SYSZ, in the git submodule build. Set the capstone parameters for both s390x host and guest. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-02s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA)David Hildenbrand3-0/+9
As with the other crypto functions, we only implement subcode 0 (query) and no actual encryption/decryption. We now implement S390_FEAT_MSA_EXT_8. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-10-02s390x/tcg: We support Miscellaneous-Instruction-Extensions Facility 2David Hildenbrand1-0/+1
We implement all relevant instructions. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-10-02s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)David Hildenbrand5-0/+59
We need new CC handling, determining the CC based on the intermediate result (64bit for MSC and MSRKC, 128bit for MSGC and MSGRKC). We want to store out2 ("low") after muls128 to r1, so add "wout_out2_r1". Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-10-02s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)David Hildenbrand2-0/+10
Just like BRANCH ON CONDITION - however the address is read from memory (always 8 bytes are read), we have to wrap the address manually. The address is read using current CPU DAT/address-space controls, just like ordinary data. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-10-02s390x/tcg: Implement MULTIPLY HALFWORD (MGH)David Hildenbrand1-0/+1
Just like MULTIPLY HALFWORD IMMEDIATE (MGHI), only the second operand (signed 16 bit) comes from memory. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-10-02s390x/tcg: Implement MULTIPLY (MG, MGRK)David Hildenbrand2-0/+15
Multiply two signed 64bit values and store the 128bit result in r1 (0-63) and r1 + 1 (64-127). Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-10-02s390x/tcg: Implement SUBTRACT HALFWORD (SGH)David Hildenbrand1-0/+1
Easy to wire up. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-10-02s390x/tcg: Implement ADD HALFWORD (AGH)David Hildenbrand2-0/+2
Easy, just like ADD HALFWORD IMMEDIATE (AGHI). Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-10-02s390x/cpumodel: S390_FEAT_MISC_INSTRUCTION_EXT -> ↵David Hildenbrand2-2/+2
S390_FEAT_MISC_INSTRUCTION_EXT2 Let's avoid confusion with the "Miscellaneous-Instruction-Extensions Facility 1" Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Cc: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20200928122717.30586-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-10-02s390x/tcg: Implement MONITOR CALLDavid Hildenbrand4-0/+48
Recent upstream Linux uses the MONITOR CALL instruction for things like BUG_ON() and WARN_ON(). We currently inject an operation exception when we hit a MONITOR CALL instruction - which is wrong, as the instruction is not glued to specific CPU features. Doing a simple WARN_ON_ONCE() currently results in a panic: [ 18.162801] illegal operation: 0001 ilc:2 [#1] SMP [ 18.162889] Modules linked in: [...] [ 18.165476] Kernel panic - not syncing: Fatal exception: panic_on_oops With a proper implementation, we now get: [ 18.242754] ------------[ cut here ]------------ [ 18.242855] WARNING: CPU: 7 PID: 1 at init/main.c:1534 [...] [ 18.242919] Modules linked in: [...] [ 18.246262] ---[ end trace a420477d71dc97b4 ]--- [ 18.259014] Freeing unused kernel memory: 4220K Reported-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200918085122.26132-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-10-02s390: guest support for diagnose 0x318Collin Walling7-0/+64
DIAGNOSE 0x318 (diag318) is an s390 instruction that allows the storage of diagnostic information that is collected by the firmware in the case of hardware/firmware service events. QEMU handles the instruction by storing the info in the CPU state. A subsequent register sync will communicate the data to the hypervisor. QEMU handles the migration via a VM State Description. This feature depends on the Extended-Length SCCB (els) feature. If els is not present, then a warning will be printed and the SCLP bit that allows the Linux kernel to execute the instruction will not be set. Availability of this instruction is determined by byte 134 (aka fac134) bit 0 of the SCLP Read Info block. This coincidentally expands into the space used for CPU entries, which means VMs running with the diag318 capability may not be able to read information regarding all CPUs unless the guest kernel supports an extended-length SCCB. This feature is not supported in protected virtualization mode. Signed-off-by: Collin Walling <walling@linux.ibm.com> Acked-by: Janosch Frank <frankja@linux.ibm.com> Acked-by: Thomas Huth <thuth@redhat.com> Acked-by: David Hildenbrand <david@redhat.com> Acked-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Message-Id: <20200915194416.107460-9-walling@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-10-02s390/sclp: add extended-length sccb support for kvm guestCollin Walling3-0/+10
As more features and facilities are added to the Read SCP Info (RSCPI) response, more space is required to store them. The space used to store these new features intrudes on the space originally used to store CPU entries. This means as more features and facilities are added to the RSCPI response, less space can be used to store CPU entries. With the Extended-Length SCCB (ELS) facility, a KVM guest can execute the RSCPI command and determine if the SCCB is large enough to store a complete reponse. If it is not large enough, then the required length will be set in the SCCB header. The caller of the SCLP command is responsible for creating a large-enough SCCB to store a complete response. Proper checking should be in place, and the caller should execute the command once-more with the large-enough SCCB. This facility also enables an extended SCCB for the Read CPU Info (RCPUI) command. When this facility is enabled, the boundary violation response cannot be a result from the RSCPI, RSCPI Forced, or RCPUI commands. In order to tolerate kernels that do not yet have full support for this feature, a "fixed" offset to the start of the CPU Entries within the Read SCP Info struct is set to allow for the original 248 max entries when this feature is disabled. Additionally, this is introduced as a CPU feature to protect the guest from migrating to a machine that does not support storing an extended SCCB. This could otherwise hinder the VM from being able to read all available CPU entries after migration (such as during re-ipl). Signed-off-by: Collin Walling <walling@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Message-Id: <20200915194416.107460-7-walling@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-10-01target/arm: Fix SVE spliceRichard Henderson1-1/+1
While converting to gen_gvec_ool_zzzp, we lost passing a->esz as the data argument to the function. Fixes: 36cbb7a8e71 Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200918000500.2690937-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01target/arm: Fix sve ldr/strRichard Henderson1-2/+2
The mte update missed a bit when producing clean addresses. Fixes: b2aa8879b88 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200916014102.2446323-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01target/arm: Make isar_feature_aa32_fp16_arith() handle M-profilePeter Maydell1-5/+26
The M-profile definition of the MVFR1 ID register differs slightly from the A-profile one, and in particular the check for "does the CPU support fp16 arithmetic" is not the same. We don't currently implement any M-profile CPUs with fp16 arithmetic, so this is not yet a visible bug, but correcting the logic now disarms this beartrap for when we eventually do. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200910173855.4068-6-peter.maydell@linaro.org
2020-10-01target/arm: Add ID register values for Cortex-M0Peter Maydell1-0/+24
Give the Cortex-M0 ID register values corresponding to its implemented behaviour. These will not be guest-visible but will be used to govern the behaviour of QEMU's emulation. We use the same values that the Cortex-M3 does. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
2020-10-01target/arm: Move id_pfr0, id_pfr1 into ARMISARegistersPeter Maydell6-38/+42
Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters sub-struct. We're going to want id_pfr1 for an isar_features check, and moving both at the same time avoids an odd inconsistency. Changes other than the ones to cpu.h and kvm64.c made automatically with: perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c hw/intc/armv7m_nvic.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200910173855.4068-3-peter.maydell@linaro.org
2020-10-01target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA checkPeter Maydell3-4/+17
The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN bit in short-descriptor translation table format descriptors. This is indicated by ID_MMFR0.VMSA being at least 0b0100. Replace the feature bit with an ID register check, in line with our preference for ID register checks over feature bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200910173855.4068-2-peter.maydell@linaro.org
2020-09-30target/i386: kvm: do not use kvm_check_extension to find paravirtual ↵Paolo Bonzini1-32/+0
capabilities Paravirtualized features have been listed in KVM_GET_SUPPORTED_CPUID since Linux 2.6.35 (commit 84478c829d0f, "KVM: x86: export paravirtual cpuid flags in KVM_GET_SUPPORTED_CPUID", 2010-05-19). It has been more than 10 years, so remove the fallback code. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-30target/i386: always create kvmclock deviceVitaly Kuznetsov2-0/+6
QEMU's kvmclock device is only created when KVM PV feature bits for kvmclock (KVM_FEATURE_CLOCKSOURCE/KVM_FEATURE_CLOCKSOURCE2) are exposed to the guest. With 'kvm=off' cpu flag the device is not created and we don't call KVM_GET_CLOCK/KVM_SET_CLOCK upon migration. It was reported that without these call at least Hyper-V TSC page clocksouce (which can be enabled independently) gets broken after migration. Switch to creating kvmclock QEMU device unconditionally, it seems to always make sense to call KVM_GET_CLOCK/KVM_SET_CLOCK on migration. Use KVM_CAP_ADJUST_CLOCK check instead of CPUID feature bits. Reported-by: Antoine Damhet <antoine.damhet@blade-group.com> Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20200922151934.899555-1-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-30target/i386: Fix VM migration when interrupt based APF is enabledVitaly Kuznetsov1-6/+6
VM with interrupt based APF enabled fails to migrate: qemu-system-x86_64: error: failed to set MSR 0x4b564d02 to 0xf3 We have two issues: 1) There is a typo in kvm_put_msrs() and we write async_pf_int_msr to MSR_KVM_ASYNC_PF_EN (instead of MSR_KVM_ASYNC_PF_INT) 2) We restore MSR_KVM_ASYNC_PF_EN before MSR_KVM_ASYNC_PF_INT is set and this violates the check in KVM. Re-order MSR_KVM_ASYNC_PF_EN/MSR_KVM_ASYNC_PF_INT setting (and kvm_get_msrs() for consistency) and fix the typo. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20200917102316.814804-1-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-30helper_syscall x86_64: clear exception_is_intDouglas Crosher1-0/+1
The exception_is_int flag may be set on entry to helper_syscall, e.g. after a prior interrupt that has returned, and processing EXCP_SYSCALL as an interrupt causes it to fail so clear this flag. Signed-off-by: Douglas Crosher <dtc-ubuntu@scieneer.com> Message-Id: <a7dab33e-eda6-f988-52e9-f3d32db7538d@scieneer.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-30i386/cpu: Clear FEAT_XSAVE_COMP_{LO,HI} when XSAVE is not availableXiaoyao Li1-0/+2
Per Intel SDM vol 1, 13.2, if CPUID.1:ECX.XSAVE[bit 26] is 0, the processor provides no further enumeration through CPUID function 0DH. QEMU does not do this for "-cpu host,-xsave". Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20200716082019.215316-2-xiaoyao.li@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-30target/i386: support KVM_FEATURE_ASYNC_PF_INTVitaly Kuznetsov4-1/+32
Linux-5.8 introduced interrupt based mechanism for 'page ready' events delivery and disabled the old, #PF based one (see commit 2635b5c4a0e4 "KVM: x86: interrupt based APF 'page ready' event delivery"). Linux guest switches to using in in 5.9 (see commit b1d405751cd5 "KVM: x86: Switch KVM guest to using interrupts for page ready APF delivery"). The feature has a new KVM_FEATURE_ASYNC_PF_INT bit assigned and the interrupt vector is set in MSR_KVM_ASYNC_PF_INT MSR. Support this in QEMU. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20200908141206.357450-1-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-30WHPX: vmware cpuid leaf for tsc and apic frequencySunil Muthuswamy2-12/+87
Newer versions of WHPX provide the capability to query the tsc and apic frequency. Expose these through the vmware cpuid leaf. This patch doesnt support setting the tsc frequency; that will come as a separate fix. Signed-off-by: Sunil Muthuswamy <sunilmut@microsoft.com> Message-Id: <SN4PR2101MB08808DFDDC3F442BBEAADFF4C0710@SN4PR2101MB0880.namprd21.prod.outlook.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-24Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell8-14/+14
staging Pull request This includes the atomic_ -> qatomic_ rename that touches many files and is prone to conflicts. # gpg: Signature made Wed 23 Sep 2020 17:08:43 BST # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: qemu/atomic.h: rename atomic_ to qatomic_ tests: add test-fdmon-epoll fdmon-poll: reset npfd when upgrading to fdmon-epoll gitmodules: add qemu.org vbootrom submodule gitmodules: switch to qemu.org meson mirror gitmodules: switch to qemu.org qboot mirror docs/system: clarify deprecation schedule virtio-crypto: don't modify elem->in/out_sg virtio-blk: undo destructive iov_discard_*() operations util/iov: add iov_discard_undo() virtio: add vhost-user-fs-ccw device libvhost-user: handle endianness as mandated by the spec MAINTAINERS: add Stefan Hajnoczi as block/nvme.c maintainer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-23qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi8-14/+14
clang's C11 atomic_fetch_*() functions only take a C11 atomic type pointer argument. QEMU uses direct types (int, etc) and this causes a compiler error when a QEMU code calls these functions in a source file that also included <stdatomic.h> via a system header file: $ CC=clang CXX=clang++ ./configure ... && make ../util/async.c:79:17: error: address argument to atomic operation must be a pointer to _Atomic type ('unsigned int *' invalid) Avoid using atomic_*() names in QEMU's atomic.h since that namespace is used by <stdatomic.h>. Prefix QEMU's APIs with 'q' so that atomic.h and <stdatomic.h> can co-exist. I checked /usr/include on my machine and searched GitHub for existing "qatomic_" users but there seem to be none. This patch was generated using: $ git grep -h -o '\<atomic\(64\)\?_[a-z0-9_]\+' include/qemu/atomic.h | \ sort -u >/tmp/changed_identifiers $ for identifier in $(</tmp/changed_identifiers); do sed -i "s%\<$identifier\>%q$identifier%g" \ $(git grep -I -l "\<$identifier\>") done I manually fixed line-wrap issues and misaligned rST tables. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200923105646.47864-1-stefanha@redhat.com>
2020-09-22s390x: Register all CPU properties as class propertiesEduardo Habkost3-21/+16
Class properties make QOM introspection simpler and easier, as they don't require an object to be instantiated. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20200921221045.699690-13-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-22qom: simplify object_find_property / object_class_find_propertyDaniel P. Berrangé3-3/+3
When debugging QEMU it is often useful to put a breakpoint on the error_setg_internal method impl. Unfortunately the object_property_add / object_class_property_add methods call object_property_find / object_class_property_find methods to check if a property exists already before adding the new property. As a result there are a huge number of calls to error_setg_internal on startup of most QEMU commands, making it very painful to set a breakpoint on this method. Most callers of object_find_property and object_class_find_property, however, pass in a NULL for the Error parameter. This simplifies the methods to remove the Error parameter entirely, and then adds some new wrapper methods that are able to raise an Error when needed. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200914135617.1493072-1-berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
generated by cgit v1.1 at 2024-10-21 10:20:38 +0000