riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-10-02	target/i386: fix translation for icount mode	Pavel Dovgalyuk	1	-3/+3
2018-10-02	hvf: drop unused variable	Paolo Bonzini	1	-1/+0
2018-10-02	i386: Compile CPUX86State xsave_buf only when support KVM or HVF	Liran Alon	5	-8/+10
2018-10-02	target/i386: rename HF_SVMI_MASK to HF_GUEST_MASK	Paolo Bonzini	5	-11/+11
2018-10-02	target/i386: unify masking of interrupts	Paolo Bonzini	3	-67/+91
2018-10-02	target/i386: move x86_64_hregs to DisasContext	Emilio G. Cota	1	-153/+154
2018-10-02	target/i386: move cpu_tmp1_i64 to DisasContext	Emilio G. Cota	1	-80/+80
2018-10-02	target/i386: move cpu_tmp3_i32 to DisasContext	Emilio G. Cota	1	-32/+32
2018-10-02	target/i386: move cpu_tmp2_i32 to DisasContext	Emilio G. Cota	1	-173/+174
2018-10-02	target/i386: move cpu_ptr1 to DisasContext	Emilio G. Cota	1	-26/+26
2018-10-02	target/i386: move cpu_ptr0 to DisasContext	Emilio G. Cota	1	-49/+52
2018-10-02	target/i386: move cpu_tmp4 to DisasContext	Emilio G. Cota	1	-39/+39
2018-10-02	target/i386: move cpu_tmp0 to DisasContext	Emilio G. Cota	1	-138/+144
2018-10-02	target/i386: move cpu_T1 to DisasContext	Emilio G. Cota	1	-171/+170
2018-10-02	target/i386: move cpu_T0 to DisasContext	Emilio G. Cota	1	-580/+594
2018-10-02	target/i386: move cpu_A0 to DisasContext	Emilio G. Cota	1	-236/+236
2018-10-02	target/i386: move cpu_cc_srcT to DisasContext	Emilio G. Cota	1	-14/+18
2018-10-02	kvm: x86: Fix kvm_arch_fixup_msi_route for remap-less case	Jan Kiszka	1	-0/+4
2018-10-01	target/xtensa: extract gen_check_interrupts call	Max Filippov	1	-25/+53
2018-10-01	target/xtensa: make rsr/wsr helpers return void	Max Filippov	1	-66/+36
2018-10-01	target/xtensa: extract unconditional TB termination via slot 0	Max Filippov	1	-47/+36
2018-10-01	target/xtensa: always end TB on CCOUNT access/CCOMPARE write	Max Filippov	1	-8/+5
2018-10-01	target/xtensa: change SR number checks to assertions	Max Filippov	1	-36/+29
2018-10-01	target/xtensa: extract unconditional TB termination	Max Filippov	1	-39/+28
2018-10-01	target/xtensa: extract test for division by zero	Max Filippov	1	-22/+31
2018-10-01	target/xtensa: extract test for cpdisabled exception	Max Filippov	2	-108/+123
2018-10-01	target/xtensa: extract test for alloca exception	Max Filippov	1	-3/+8
2018-10-01	target/xtensa: extract test for window underflow exception	Max Filippov	3	-9/+25
2018-10-01	target/xtensa: extract test for window overflow exception	Max Filippov	3	-587/+889
2018-10-01	target/xtensa: extract test for debug exception	Max Filippov	1	-10/+13
2018-10-01	target/xtensa: extract test for syscall instruction	Max Filippov	1	-7/+6
2018-10-01	target/xtensa: extract test for privileged instruction	Max Filippov	1	-93/+294
2018-10-01	target/xtensa: extract test for an illegal instruction	Max Filippov	5	-73/+400
2018-09-25	target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode	Peter Maydell	1	-2/+12
2018-09-25	target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs	Richard Henderson	1	-21/+24
2018-09-25	Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180925' into...	Peter Maydell	1	-21/+19
2018-09-25	Merge remote-tracking branch 'remotes/xtensa/tags/20180918-xtensa' into staging	Peter Maydell	12	-51/+46155
2018-09-25	target/ppc/cpu-models: Re-group the 970 CPUs together again	Thomas Huth	1	-21/+19
2018-09-24	Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180907' into...	Peter Maydell	6	-58/+21
2018-09-24	Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-pullreq-201809...	Peter Maydell	4	-56/+64
2018-09-17	target/xtensa: support input from chardev console	Max Filippov	1	-10/+61
2018-09-17	target/xtensa: fix s32c1i TCGMemOp flags	Max Filippov	1	-1/+1
2018-09-17	target/xtensa: fix FPU2000 bugs	Max Filippov	1	-3/+3
2018-09-17	target/xtensa: convert to do_transaction_failed	Max Filippov	4	-16/+35
2018-09-05	riscv: remove define cpu_init()	Igor Mammedov	1	-1/+0
2018-09-05	target/riscv: call gen_goto_tb on DISAS_TOO_MANY	Emilio G. Cota	1	-6/+1
2018-09-05	target/riscv: optimize indirect branches	Emilio G. Cota	1	-1/+1
2018-09-05	target/riscv: optimize cross-page direct jumps in softmmu	Emilio G. Cota	1	-1/+1
2018-09-05	target/ppc/kvm: set vcpu as online/offline	Nikunj A Dadhania	2	-0/+16
2018-09-04	RISC-V: Simplify riscv_cpu_local_irqs_pending	Michael Clark	1	-22/+12