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2017-12-14s390x: change the QEMU cpu model to a stripped down z12David Hildenbrand4-59/+139
We are good enough to boot upstream Linux kernels / Fedora 26/27. That should be sufficient for now. As the QEMU CPU model is migration safe, let's add compatibility code. Generate the feature list to reduce the chance of messing things up in the future. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208165529.14124-1-david@redhat.com> [CH: squashed 's390x/cpumodel: make qemu cpu model play with "none" machine' (20171213132407.5227-1-david@redhat.com) and 's390x/tcg: don't include z13 features in the qemu model' (20171213171512.17601-1-david@redhat.com) into patch] Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: we already implement the Set-Program-Parameter facilityDavid Hildenbrand1-2/+3
The Set-Program-Parameter facility (also known as Load-Program-Parameter facility) provides the LPP instruction used to load the program parameter. We already implement that instruction in TCG, so add it to our list. Note: Not documented in the PoP but in "The Load-Program-Parameter and CPU-Measurement Facilities) - SA23-2260-05 document. While at it, make the whole list ordered (according to cpu_features_def.h). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: implement extract-CPU-time facilityDavid Hildenbrand5-7/+50
It only provides the EXTRACT CPU TIME instruction. We can reuse the stpt helper, which calculates the CPU timer value. As the instruction is not privileged, but we don't have a CPU timer value in case of linux user, we simply reuse cpu_get_host_ticks() to produce some descending value. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: Implement SIGNAL ADAPTER instructionDavid Hildenbrand2-0/+9
KVM suppresses SIGA, setting cc=3. Let's do the same for TCG, so we're at least equal. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: Implement STORE CHANNEL PATH STATUSDavid Hildenbrand2-0/+8
Just like KVM does, we should suppress this instruction: When this instruction is not provided, it is checked for privileged operation exception and the instruction is suppressed by the machine Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: wire up SET CHANNEL MONITORDavid Hildenbrand4-0/+18
Let's just wire it up like KVM. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: wire up SET ADDRESS LIMITDavid Hildenbrand4-0/+18
Let's handle it just like KVM: Depending on the model, this instruction may not be provided. When this instruction is not provided, it is checked for operand exception and privileged-opera- tion exception, and then is suppressed. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: implement Interlocked-Access Facility 2David Hildenbrand3-6/+70
With this facility, OI/OIY, NI/NIY and XI/XIY are atomic. All operate on one byte (MO_UB). Emulate old behavior. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: ASI/ASGI/ALSI/ALSGI are atomic with Interlocked-acccess facility 1David Hildenbrand2-4/+25
The semantics of ASI/ASGI/ALSI/ALSGI changed. Let's implement them just like LOAD AND ADD, so they are atomic. Emulate old behavior. This fixes random crashes when booting a Linux kernel compiled for z196+ with SMP + MTTCG. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: wire up STORE CHANNEL REPORT WORDDavid Hildenbrand4-0/+19
CRW machine check handling requires STCRW. So let's wire it up. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: indicate value of TODPR in STCKEDavid Hildenbrand1-0/+5
We were not yet using the value of the TOD Programmable Register. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: implement SET CLOCK PROGRAMMABLE FIELDDavid Hildenbrand4-0/+21
Needed for machine check handling inside Linux (when restoring registers). Except for SIGP and machine checks, we don't make use of the register yet. Sufficient for now. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-4-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: fix and cleanup mcck injectionDavid Hildenbrand2-9/+9
The architecture mode indication wasn't stored. The split of certain 64bit fields was unnecessary. Also, the complete clock comparator, not just bit 0-55 (starting at byte 1) was stored. We now generate a proper MCIC via the same helper we use for KVM. There is more to clean up, but we will change the other parts later on either way. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/kvm: factor out build_channel_report_mcic() into cpu.hDavid Hildenbrand2-23/+25
We'll need it later on in two places. Refactor it to just indicate the validity bits. While at it, introduce a define for the used CR14 bit (we'll also need later on). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-2-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: drop potential_page_fault()David Hildenbrand1-7/+2
Only one user left, get rid of it so we don't get any new users. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: drop program_interrupt()David Hildenbrand2-18/+5
All users are gone, we can finally drop it and make sure that all new program interrupt injections are reminded of the retaddr - as they have to use s390_program_interrupt() now. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-16-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: use s390_program_interrupt() in STSIDavid Hildenbrand2-2/+1
STSI needs some more love, but let's do one step at a time. We can now drop potential_page_fault(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: use s390_program_interrupt() in SACFDavid Hildenbrand1-1/+1
Convert this user, too. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: use s390_program_interrupt() in per_check_exception()David Hildenbrand2-4/+1
We can now drop updating the cc. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: use s390_program_interrupt() in DIAGDavid Hildenbrand2-4/+1
Now we can drop the two save statements in the translate function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: use s390_program_interrupt() in SCLP Service CallDavid Hildenbrand2-4/+2
Now we can drop potential_page_fault(). While at it, move the unlock further up, looks cleaner. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: io instructions don't need potential_page_fault()David Hildenbrand1-10/+0
As we handle the retaddr in all cases properly now, we can drop it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: don't exit the cpu loop in s390_cpu_virt_mem_rw()David Hildenbrand1-3/+6
s390_cpu_virt_mem_rw() must always return, so callers can react on an exception (e.g. see ioinst_handle_stcrw()). Therefore, using program_interrupt() is wrong. Fix that up. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x: handle exceptions during s390_cpu_virt_mem_rw() correctly (TCG)David Hildenbrand3-3/+32
s390_cpu_virt_mem_rw() must always return, so callers can react on an exception (e.g. see ioinst_handle_stcrw()). However, for TCG we always have to exit the cpu loop (and restore the cpu state before that) if we injected a program interrupt. So let's introduce and use s390_cpu_virt_mem_handle_exc() in code that is not purely KVM. Directly pass the retaddr we already have available in these functions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/diag: pass the retaddr into handle_diag_308()David Hildenbrand4-10/+11
Needed to later drop potential_page_fault() from the diag TCG translate function. Convert program_interrupt() to s390_program_interrupt() directly, making use of the passed address. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/pci: pass the retaddr to all PCI instructionsDavid Hildenbrand1-7/+7
Once we wire up TCG, we will need the retaddr to correctly inject program interrupts. As we want to get rid of the function program_interrupt(), convert PCI code too. For KVM, we can simply use RA_IGNORED. Convert program_interrupt() to s390_program_interrupt() directly, making use of the passed address. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/ioinst: pass the retaddr to all IO instructionsDavid Hildenbrand5-69/+75
TCG needs the retaddr when injecting an interrupt. Let's just pass it along and use RA_IGNORED for KVM. The value will be completely ignored for KVM. Convert program_interrupt() to s390_program_interrupt() directly, making use of the passed address. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: rip out dead tpi codeDavid Hildenbrand2-27/+0
It is broken and not even wired up. We'll add a new handler soon, but that will live somewhere else. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: get rid of runtime_exception()David Hildenbrand4-26/+8
Let's use s390_program_interrupt() instead. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: introduce and use s390_program_interrupt()David Hildenbrand6-35/+30
Allows to easily convert more callers of program_interrupt() and to easily introduce new exceptions without forgetting about the cpu state reset. Use s390_program_interrupt() in places where we already had the same pattern. We will later get rid of program_interrupt(). RA != 0 checks are already done behind the scenes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14target/s390x: nuke DPRINTF in helper.cCornelia Huck1-18/+0
It is not used anywhere. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/migration: use zero flag parameterChristian Borntraeger1-8/+8
valgrind pointed out that we call KVM_S390_GET_IRQ_STATE with an undefined value for flags. Kernels prior to 4.15 did not use that field, and later kernels ignore it for compatibility reasons, but we better play safe. The same is true for SET_IRQ_STATE. We should make sure to not use the flag field, either. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20171122142627.73170-2-borntraeger@de.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-13target/arm: Extend PAR format determinationEdgar E. Iglesias1-4/+29
Now that do_ats_write() is entirely in control of whether to generate a 32-bit PAR or a 64-bit PAR, we can make it use the correct (complicated) condition for doing so. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1512503192-2239-13-git-send-email-peter.maydell@linaro.org [PMM: Rebased Edgar's patch on top of get_phys_addr() refactoring; use arm_s1_regime_using_lpae_format() rather than regime_using_lpae_format() because the latter will assert if passed ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1; updated commit message appropriately] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-12-13target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill()Peter Maydell3-34/+16
All of the callers of get_phys_addr() and arm_tlb_fill() now ignore the FSR values they return, so we can just remove the argument entirely. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Message-id: 1512503192-2239-12-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Ignore fsr from get_phys_addr() in do_ats_write()Peter Maydell1-6/+10
In do_ats_write(), rather than using the FSR value from get_phys_addr(), construct the PAR values using the information in the ARMMMUFaultInfo struct. This allows us to create a PAR of the correct format regardless of what the translation table format is. For the moment we leave the condition for "when should this be a 64 bit PAR" as it was previously; this will need to be fixed to properly support AArch32 Hyp mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Message-id: 1512503192-2239-11-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Use ARMMMUFaultInfo in deliver_fault()Peter Maydell1-57/+22
Now that ARMMMUFaultInfo is guaranteed to have enough information to construct a fault status code, we can pass it in to the deliver_fault() function and let it generate the correct type of FSR for the destination, rather than relying on the value provided by get_phys_addr(). I don't think there are any cases the old code was getting wrong, but this is more obviously correct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Message-id: 1512503192-2239-10-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Convert get_phys_addr_pmsav8() to not return FSC valuesPeter Maydell1-11/+18
Make get_phys_addr_pmsav8() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Message-id: 1512503192-2239-9-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Convert get_phys_addr_pmsav7() to not return FSC valuesPeter Maydell1-4/+7
Make get_phys_addr_pmsav7() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Message-id: 1512503192-2239-8-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Convert get_phys_addr_pmsav5() to not return FSC valuesPeter Maydell1-7/+13
Make get_phys_addr_pmsav5() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Note that PMSAv5 does not define any guest-visible fault status register, so the different "fsr" values we were previously returning are entirely arbitrary. So we can just switch to using the most appropriae fi->type values without worrying that we need to special-case FaultInfo->FSC conversion for PMSAv5. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Message-id: 1512503192-2239-7-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Convert get_phys_addr_lpae() to not return FSC valuesPeter Maydell1-23/+18
Make get_phys_addr_v6() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Message-id: 1512503192-2239-6-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Convert get_phys_addr_v6() to not return FSC valuesPeter Maydell1-18/+22
Make get_phys_addr_v6() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Message-id: 1512503192-2239-5-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Convert get_phys_addr_v5() to not return FSC valuesPeter Maydell1-15/+18
Make get_phys_addr_v5() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Message-id: 1512503192-2239-4-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Remove fsr argument from arm_ld*_ptw()Peter Maydell1-13/+11
All the callers of arm_ldq_ptw() and arm_ldl_ptw() ignore the value that those functions store in the fsr argument on failure: if they return failure to their callers they will always overwrite the fsr value with something else. Remove the argument from these functions and S1_ptw_translate(). This will simplify removing fsr from the calling functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Message-id: 1512503192-2239-3-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Provide fault type enum and FSR conversion functionsPeter Maydell1-0/+185
Currently get_phys_addr() and its various subfunctions return a hard-coded fault status register value for translation failures. This is awkward because FSR values these days may be either long-descriptor format or short-descriptor format. Worse, the right FSR type to use doesn't depend only on the translation table being walked -- some cases, like fault info reported to AArch32 EL2 for some kinds of ATS operation, must be in long-descriptor format even if the translation table being walked was short format. We can't get those cases right with our current approach. Provide fields in the ARMMMUFaultInfo struct which allow get_phys_addr() to provide sufficient information for a caller to construct an FSR value themselves, and utility functions which do this for both long and short format FSR values, as a first step in switching get_phys_addr() and its children to only returning the failure cause in the ARMMMUFaultInfo struct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Message-id: 1512503192-2239-2-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Implement TT instructionPeter Maydell3-1/+138
Implement the TT instruction which queries the security state and access permissions of a memory location. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1512153879-5291-8-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Factor MPU lookup code out of get_phys_addr_pmsav8()Peter Maydell1-51/+79
For the TT instruction we're going to need to do an MPU lookup that also tells us which MPU region the access hit. This requires us to do the MPU lookup without first doing the SAU security access check, so pull the MPU lookup parts of get_phys_addr_pmsav8() out into their own function. The TT instruction also needs to know the MPU region number which the lookup hit, so provide this information to the caller of the MPU lookup code, even though get_phys_addr_pmsav8() doesn't need to know it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1512153879-5291-7-git-send-email-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-12-13target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv()Peter Maydell1-5/+16
The TT instruction is going to need to look up the MMU index for a specified security and privilege state. Refactor the existing arm_v7m_mmu_idx_for_secstate() into a version that lets you specify the privilege state and one that uses the current state of the CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1512153879-5291-6-git-send-email-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-12-13target/arm: Split M profile MNegPri mmu index into user and privPeter Maydell4-29/+50
For M profile, we currently have an mmu index MNegPri for "requested execution priority negative". This fails to distinguish "requested execution priority negative, privileged" from "requested execution priority negative, usermode", but the two can return different results for MPU lookups. Fix this by splitting MNegPri into MNegPriPriv and MNegPriUser, and similarly for the Secure equivalent MSNegPri. This takes us from 6 M profile MMU modes to 8, which means we need to bump NB_MMU_MODES; this is OK since the point where we are forced to reduce TLB sizes is 9 MMU modes. (It would in theory be possible to stick with 6 MMU indexes: {mpu-disabled,user,privileged} x {secure,nonsecure} since in the MPU-disabled case the result of an MPU lookup is always the same for both user and privileged code. However we would then need to rework the TB flags handling to put user/priv into the TB flags separately from the mmuidx. Adding an extra couple of mmu indexes is simpler.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1512153879-5291-5-git-send-email-peter.maydell@linaro.org
2017-12-13target/arm: Add missing M profile case to regime_is_user()Peter Maydell1-0/+1
When we added the ARMMMUIdx_MSUser MMU index we forgot to add it to the case statement in regime_is_user(), so we weren't treating it as unprivileged when doing MPU lookups. Correct the omission. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1512153879-5291-4-git-send-email-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-12-13target/arm: Allow explicit writes to CONTROL.SPSEL in Handler modePeter Maydell1-1/+4
In ARMv7M the CPU ignores explicit writes to CONTROL.SPSEL in Handler mode. In v8M the behaviour is slightly different: writes to the bit are permitted but will have no effect. We've already done the hard work to handle the value in CONTROL.SPSEL being out of sync with what stack pointer is actually in use, so all we need to do to fix this last loose end is to update the condition we use to guard whether we call write_v7m_control_spsel() on the register write. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1512153879-5291-3-git-send-email-peter.maydell@linaro.org
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