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2023-05-05target/riscv: remove cpu->cfg.ext_cDaniel Henrique Barboza2-6/+4
Create a new "c" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are replaced with riscv_has_ext(env, RVC). Remove the old "c" property and 'ext_c' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_aDaniel Henrique Barboza2-9/+8
Create a new "a" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are replaced with riscv_has_ext(env, RVA). Remove the old "a" property and 'ext_a' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: introduce riscv_cpu_add_misa_properties()Daniel Henrique Barboza1-0/+65
Ever since RISCVCPUConfig got introduced users are able to set CPU extensions in the command line. User settings are reflected in the cpu->cfg object for later use. These properties are used in the target/riscv/cpu.c code, most notably in riscv_cpu_validate_set_extensions(), where most of our realize time validations are made. And then there's env->misa_ext, the field where the MISA extensions are set, that is read everywhere else. We need to keep env->misa_ext updated with cpu->cfg settings, since our validations rely on it, forcing us to make register_cpu_props() write cpu->cfg.ext_N flags to cover for named CPUs that aren't used named properties but also needs to go through the same validation steps. Failing to so will make those name CPUs fail validation (see c66ffcd5358b for more info). Not only that, but we also need to sync env->misa_ext with cpu->cfg again during realize() time to catch any change the user might have done, since the rest of the code relies on that. Making cpu->cfg.ext_N and env->misa_ext reflect each other is not needed. What we want is a way for users to enable/disable MISA extensions, and there's nothing stopping us from letting the user write env->misa_ext directly. Here are the artifacts that will enable us to do that: - RISCVCPUMisaExtConfig will declare each MISA property; - cpu_set_misa_ext_cfg() is the setter for each property. We'll write env->misa_ext and env->misa_ext_mask with the appropriate misa_bit; cutting off cpu->cfg.ext_N from the logic; - cpu_get_misa_ext_cfg() is a getter that will retrieve the current val of the property based on env->misa_ext; - riscv_cpu_add_misa_properties() will be called in register_cpu_props() to init all MISA properties from the misa_ext_cfgs[] array. With this infrastructure we'll start to get rid of each cpu->cfg.ext_N attribute in the next patches. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv/cpu.c: remove 'multi_letter' from isa_ext_dataDaniel Henrique Barboza1-67/+65
We don't have MISA extensions in isa_edata_arr[] anymore. Remove the redundant 'multi_letter' field from isa_ext_data. Suggested-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove MISA properties from isa_edata_arr[]Daniel Henrique Barboza1-2/+17
The code that disables extensions if there's a priv version mismatch uses cpu->cfg.ext_N properties to do its job. We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split the MISA related verifications in a new function, removing it from isa_edata_arr[]. We're also erroring it out instead of disabling, making the cpu_init() function responsible for running an adequate priv spec for the MISA extensions it wants to use. Note that the RVV verification is being ignored since we're always have at least PRIV_VERSION_1_10_0. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: sync env->misa_ext* with cpu->cfg in realize()Daniel Henrique Barboza1-38/+56
When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N properties updated. The same can't be said about env->misa_ext*, since the user might enable/disable MISA extensions in the command line, and env->misa_ext* won't caught these changes. The current solution is to sync everything at the end of validate_set_extensions(), checking every cpu->cfg.ext_N value to do a set_misa() in the end. The last change we're making in the MISA cfg flags are in the G extension logic, enabling IMAFG if cpu->cfg_ext.g is enabled. Otherwise we're not making any changes in MISA bits ever since realize() starts. There's no reason to postpone misa_ext updates until the end of the validation. Let's do it earlier, during realize(), in a new helper called riscv_cpu_sync_misa_cfg(). If cpu->cfg.ext_g is enabled, do it again by updating env->misa_ext* directly. This is a pre-requisite to allow riscv_cpu_validate_set_extensions() to use riscv_has_ext() instead of cpu->cfg.ext_N to validate the MISA extensions, which is our end goal here. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li9-56/+91
Fix lines with over 80 characters for both code and comments. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix format for commentsWeiwei Li11-104/+151
Fix formats for multi-lines comments. Add spaces around single line comments(after "/*" and before "*/"). Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix format for indentationWeiwei Li12-241/+247
Fix identation problems, and try to use the same indentation strategy in the same file. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li8-70/+64
Directly use env->virt_enabled instead. Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Set opcode to env->bins for illegal/virtual instruction faultWeiwei Li1-0/+2
decode_save_opc() will not work for generate_exception(), since 0 is passed to riscv_raise_exception() as pc in helper_raise_exception(), and bins will not be restored in this case. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230330034636.44585-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix addr type for get_physical_addressWeiwei Li1-2/+2
Function get_physical_address() translates both virtual address and guest physical address, and the latter is 34-bits for Sv32x4. So we should use vaddr type for 'addr' parameter. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230329101928.83856-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Remove redundant parenthesesWeiwei Li1-1/+1
Remove redundant parentheses in get_physical_address. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230327080858.39703-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei5-12/+9
Currently we only use the env->virt to encode the virtual mode enabled status. Let's make it a bool type. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230325145348.1208-1-zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230327080858.39703-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabledWeiwei Li1-4/+1
In current implementation, riscv_cpu_set_virt_enabled is only called when RVH is enabled. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230327080858.39703-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_virt_enabledWeiwei Li1-4/+0
Since env->virt.VIRT_ONOFF is initialized as false, and will not be set to true when RVH is disabled, so we can just return this bit(false) when RVH is not disabled. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230327080858.39703-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Remove redundant check on RVHWeiwei Li1-2/+1
Check on riscv_cpu_virt_enabled contains the check on RVH. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230327080858.39703-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Remove redundant call to riscv_cpu_virt_enabledWeiwei Li1-3/+1
The assignment is done under the condition riscv_cpu_virt_enabled()=true. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230327080858.39703-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix itrigger when icount is usedLIU Zhiwei1-0/+6
When I boot a ubuntu image, QEMU output a "Bad icount read" message and exit. The reason is that when execute helper_mret or helper_sret, it will cause a call to icount_get_raw_locked (), which needs set can_do_io flag on cpustate. Thus we setting this flag when execute these two instructions. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230324064011.976-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Add support for ZceWeiwei Li2-0/+13
Add and expose property for Zce: * Specifying Zce without F includes Zca, Zcb, Zcmp, Zcmt. * Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-11-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: expose properties for Zc* extensionWeiwei Li1-0/+14
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-9-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li9-5/+157
Add encode, trans* functions and helper functions support for Zcmt instrutions. Add support for jvt csr. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li3-1/+209
Add encode, trans* functions for Zcmp instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li3-0/+125
Add encode and trans* functions support for Zcb instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add support for Zcd extensionWeiwei Li2-4/+22
Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add support for Zcf extensionWeiwei Li2-4/+22
Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add support for Zca extensionWeiwei Li2-4/+8
Modify the check for C extension to Zca (C implies Zca). Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-Id: <20230307081403.61950-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add cfg properties for Zc* extensionWeiwei Li2-0/+49
Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension. Add check for these properties. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: fix invalid riscv,event-to-mhpmcounters entryConor Dooley1-1/+1
dt-validate complains: > soc: pmu: {'riscv,event-to-mhpmcounters': > [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280], > [65563, 65563, 524280], [65569, 65569, 524280], [0, 0, 0], [0, 0]], > pmu: riscv,event-to-mhpmcounters:6: [0, 0] is too short There are bogus 0 entries added at the end, of which one is of insufficient length. This happens because only 15 of fdt_event_ctr_map[]'s 20 elements are populated & qemu_fdt_setprop() is called using the size of the array. Reduce the array to 15 elements to make the error go away. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230404173333.35179-1-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: redirect XVentanaCondOps to use the Zicond functionsPhilipp Tomsich1-15/+3
The Zicond standard extension implements the same instruction semantics as XVentanaCondOps, although using different mnemonics and opcodes. Point XVentanaCondOps to the (newly implemented) Zicond implementation to reduce the future maintenance burden. Also updating MAINTAINERS as trans_xventanacondops.c.inc. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307180708.302867-3-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: refactor Zicond supportPhilipp Tomsich1-15/+21
After the original Zicond support was stuck/fell through the cracks on the mailing list at v3 (and a different implementation was merged in the meanwhile), we need to refactor Zicond to prepare it to be reused by XVentanaCondOps. This commit lifts the common logic out into gen_czero and uses this via gen_logic and 2 helper functions (effectively partial closures). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307180708.302867-2-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Simplify arguments for riscv_csrrw_checkWeiwei Li1-8/+4
Remove RISCVCPU argument, and get cfg infomation from CPURISCVState directly. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230309071329.45932-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li7-44/+31
Use CPURISCVState as argument directly in riscv_cpu_update_mip and riscv_timer_write_timecmp, since type converts from CPURISCVState to RISCVCPU in many caller of them and then back to CPURISCVState in them. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Simplify getting RISCVCPU pointer from envWeiwei Li1-4/+4
Use env_archcpu() to get RISCVCPU pointer from env directly. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230309071329.45932-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix priv version dependency for vector and zfhLIU Zhiwei1-4/+4
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector only requires PRIV_1_10_0, these sub extensions should not require priv version higher than that. The same for Zfh. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230321043415.754-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Avoid env_archcpu() when reading RISCVCPUConfigWeiwei Li3-35/+18
Use riscv_cpu_cfg(env) instead of env_archcpu().cfg. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230309071329.45932-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-02target/arm: Add compile time asserts to load/store_cpu_field macrosPeter Maydell1-4/+13
Add some compile-time asserts to the load_cpu_field() and store_cpu_field() macros that the struct field being accessed is the expected size. This lets us catch cases where we incorrectly tried to do a 32-bit load from a 64-bit struct field. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230424153909.1419369-3-peter.maydell@linaro.org
2023-05-02target/arm: Define and use new load_cpu_field_low32()Peter Maydell2-2/+9
In several places in the 32-bit Arm translate.c, we try to use load_cpu_field() to load from a CPUARMState field into a TCGv_i32 where the field is actually 64-bit. This works on little-endian hosts, but gives the wrong half of the register on big-endian. Add a new load_cpu_field_low32() which loads the low 32 bits of a 64-bit field into a TCGv_i32. The new macro includes a compile-time check against accidentally using it on a field of the wrong size. Use it to fix the two places in the code where we were using load_cpu_field() on a 64-bit field. This fixes a bug where on big-endian hosts the guest would crash after executing an ERET instruction, and a more corner case one where some UNDEFs for attempted accesses to MSR banked registers from Secure EL1 might go to the wrong EL. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230424153909.1419369-2-peter.maydell@linaro.org
2023-05-02arm/Kconfig: Always select SEMIHOSTING when TCG is presentFabiano Rosas1-0/+7
We are about to enable the build without TCG, so CONFIG_SEMIHOSTING and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in default.mak anymore. So reflect the change in a Kconfig. Instead of using semihosting/Kconfig, use a target-specific file, so that the change doesn't affect other architectures which might implement semihosting in a way compatible with KVM. The selection from ARM_v7M needs to be removed to avoid a cycle during parsing. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230426180013.14814-11-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-02target/arm: move cpu_tcg to tcg/cpu32.cClaudio Fontana4-12/+5
move the module containing cpu models definitions for 32bit TCG-only CPUs to tcg/ and rename it for clarity. Signed-off-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230426180013.14814-8-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-02target/arm: Move 64-bit TCG CPUs into tcg/Fabiano Rosas4-684/+731
Move the 64-bit CPUs that are TCG-only: - cortex-a35 - cortex-a55 - cortex-a72 - cortex-a76 - a64fx - neoverse-n1 Keep the CPUs that can be used with KVM: - cortex-a57 - cortex-a53 - max - host Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230426180013.14814-6-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-02target/arm: Do not expose all -cpu max features to qtestsFabiano Rosas1-3/+9
We're about to move the TCG-only -cpu max configuration code under CONFIG_TCG. To be able to do that we need to make sure the qtests still have some cpu configured even when no other accelerator is available. Delineate now what is used with TCG-only and what is also used with qtests to make the subsequent patches cleaner. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230426180013.14814-5-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-02target/arm: Extract TCG -cpu max code into a functionFabiano Rosas1-14/+18
Introduce aarch64_max_tcg_initfn that contains the TCG-only part of -cpu max configuration. We'll need that to be able to restrict this code to a TCG-only config in the next patches. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Message-id: 20230426180013.14814-4-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-02target/arm: Remove dead code from cpu_max_set_sve_max_vqFabiano Rosas1-6/+0
The sve-max-vq property has been removed from the -cpu max used with KVM, so code under kvm_enabled in cpu_max_set_sve_max_vq is not reachable. Fixes: 0baa21be49 ("target/arm: Make KVM -cpu max exactly like -cpu host") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Message-id: 20230426180013.14814-3-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-02target/arm: Move cortex sysregs into a separate fileFabiano Rosas6-65/+77
The file cpu_tcg.c is about to be moved into the tcg/ directory, so move the register definitions into a new file. Also move the function declaration to the more appropriate cpregs.h. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230426180013.14814-2-farosas@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-04-29Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson3-8/+53
* Fix compilation issues under Debian 10 * Update kernel headers to 6.3rc5 * Suppress GCC13 false positive in aio_bh_poll() * Add new x86 feature bits * Coverity fixes * More steps towards removing qatomic_mb_set/read * Fix reduced-phys-bits value for AMD SEV # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmRNC0IUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNo0wgArWNGKZpbmQ0e5L6ajMvaaPmg4mVL # a2SJGU0TwTp0fUgZr14z2iwzIpSqQrsqhzTIAzOTs0OICDBPBuNvnRucMa+SVQGO # Tc89YAwBVDo66dAKhWi+WR9tx7sTFCso0nbsBfczzdnwAw3g1MJ87Ueqc5tlPGBK # E7YSAD6l4UuogoN5BLU7bSsG/X7bwcyzeUXRB4ik+Z9abWd4DH9qiROnBKLMmBLK # nAi47h8b8MltWORpO+wf6HtkMKi37SAzl9VLHVuHcRhIdY/JhWCRhYSo0HXhgX66 # JLVkyxFpIndT0dUW/xnqATGez92FRZyTxHbxbAcWM0SoC1jOVfUXB+7Gdw== # =vxou # -----END PGP SIGNATURE----- # gpg: Signature made Sat 29 Apr 2023 01:19:14 PM BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: cpus-common: stop using mb_set/mb_read async: Suppress GCC13 false positive in aio_bh_poll() tests: vhost-user-test: release mutex on protocol violation Update linux headers to v6.3rc5 update-linux-headers.sh: Add missing kernel headers. Fix libvhost-user.c compilation. target/i386: Add support for PREFETCHIT0/1 in CPUID enumeration target/i386: Add support for AVX-NE-CONVERT in CPUID enumeration target/i386: Add support for AVX-VNNI-INT8 in CPUID enumeration target/i386: Add support for AVX-IFMA in CPUID enumeration target/i386: Add support for AMX-FP16 in CPUID enumeration target/i386: Add support for CMPCCXADD in CPUID enumeration i386/cpu: Update how the EBX register of CPUID 0x8000001F is set i386/sev: Update checks and information related to reduced-phys-bits qemu-options.hx: Update the reduced-phys-bits documentation qapi, i386/sev: Change the reduced-phys-bits value from 5 to 1 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-28target/i386: Add support for PREFETCHIT0/1 in CPUID enumerationJiaxi Chen2-1/+3
Latest Intel platform Granite Rapids has introduced a new instruction - PREFETCHIT0/1, which moves code to memory (cache) closer to the processor depending on specific hints. The bit definition: CPUID.(EAX=7,ECX=1):EDX[bit 14] Add CPUID definition for PREFETCHIT0/1. Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20230303065913.1246327-7-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-04-28target/i386: Add support for AVX-NE-CONVERT in CPUID enumerationJiaxi Chen2-1/+3
AVX-NE-CONVERT is a new set of instructions which can convert low precision floating point like BF16/FP16 to high precision floating point FP32, as well as convert FP32 elements to BF16. This instruction allows the platform to have improved AI capabilities and better compatibility. The bit definition: CPUID.(EAX=7,ECX=1):EDX[bit 5] Add CPUID definition for AVX-NE-CONVERT. Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20230303065913.1246327-6-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-04-28target/i386: Add support for AVX-VNNI-INT8 in CPUID enumerationJiaxi Chen2-1/+25
AVX-VNNI-INT8 is a new set of instructions in the latest Intel platform Sierra Forest, aims for the platform to have superior AI capabilities. This instruction multiplies the individual bytes of two unsigned or unsigned source operands, then adds and accumulates the results into the destination dword element size operand. The bit definition: CPUID.(EAX=7,ECX=1):EDX[bit 4] AVX-VNNI-INT8 is on a new feature bits leaf. Add a CPUID feature word FEAT_7_1_EDX for this leaf. Add CPUID definition for AVX-VNNI-INT8. Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20230303065913.1246327-5-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-04-28target/i386: Add support for AVX-IFMA in CPUID enumerationJiaxi Chen2-1/+3
AVX-IFMA is a new instruction in the latest Intel platform Sierra Forest. This instruction packed multiplies unsigned 52-bit integers and adds the low/high 52-bit products to Qword Accumulators. The bit definition: CPUID.(EAX=7,ECX=1):EAX[bit 23] Add CPUID definition for AVX-IFMA. Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20230303065913.1246327-4-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2025-01-21 17:18:38 +0000