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2018-07-03target/ppc: Remove POWERPC_EXCP_STCXRichard Henderson2-19/+0
Always use the gen_conditional_store implementation that uses atomic_cmpxchg. Make sure and clear reserve_addr across most interrupts crossing the cpu_loop. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Use atomic cmpxchg for STQCXRichard Henderson3-33/+100
When running in a parallel context, we must use a helper in order to perform the 128-bit atomic operation. When running in a serial context, do the compare before the store. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Use atomic store for STQRichard Henderson3-8/+45
Section 1.4 of the Power ISA v3.0B states that this insn is single-copy atomic. As we cannot (yet) issue 128-bit stores within TCG, use the generic helpers provided. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Use atomic load for LQ and LQARXRichard Henderson4-25/+94
Section 1.4 of the Power ISA v3.0B states that both of these instructions are single-copy atomic. As we cannot (yet) issue 128-bit loads within TCG, use the generic helpers provided. Since TCG cannot (yet) return a 128-bit value, add a slot within CPUPPCState for returning the high half of a 128-bit return value. This solution is preferred to the helper assigning to architectural registers directly, as it avoids clobbering all TCG live values. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Add do_unaligned_access hookRichard Henderson3-1/+23
This allows faults from MO_ALIGN to have the same effect as from gen_check_align. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-02s390x/tcg: fix locking problem with tcg_s390_tod_updatedDavid Hildenbrand1-10/+16
tcg_s390_tod_updated() is always called with the iothread being locked (e.g. from S390TODClass->set() e.g. via HELPER(sck) or on incoming migration). The helper we call takes the lock itself - bad. Let's change that by factoring out updating the ckc timer. This now looks much nicer than having to call a helper from another function. While touching it we also make sure that env->ckc is updated even if the new value is -1ULL, for now it would not have been modified in that case. Reported-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180629170520.13671-1-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/kvm: indicate alignment in legacy_s390_alloc()David Hildenbrand1-0/+3
Let's do this for completeness reason, although we don't support e.g. PCDIMM/NVDIMM, which would use the alignment for placing the memory region in guest physical memory. But maybe someday we would want to support something like this - then we don't forget about this if allowing multiple allocations in legacy_s390_alloc(). Use the same alignment as we would set in qemu_anon_ram_alloc(). Our fixed address satisfies this alignment (1MB). This implicitly sets the alignment of the underlying memory region. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180628113817.30814-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/kvm: legacy_s390_alloc() only supports one allocationDavid Hildenbrand1-2/+10
We always allocate at a fixed address, a second allocation can therefore of course never work. We would simply overwrite mappings. This can e.g. happen in s390_memory_init(), if trying to allocate more than > 8TB. Let's just bail out, as there is no need for supporting it (legacy handling for z/VM). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180628113817.30814-2-david@redhat.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/tcg: fix CPU hotplug with single-threaded TCGDavid Hildenbrand1-5/+12
run_on_cpu() doesn't seem to work reliably until the CPU has been fully created if the single-threaded TCG main loop is already running. Therefore, hotplugging a CPU under single-threaded TCG does currently not work. We should use the direct call instead of going via run_on_cpu(). So let's use run_on_cpu() for KVM only - KVM requires it due to the initial CPU reset ioctl. As a nice side effect, we get rid of the ifdef. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/tcg: rearm the CKC timer during migrationDavid Hildenbrand3-0/+27
If the CPU data is migrated after the TOD clock, the CKC timer of a CPU is not rearmed. Let's rearm it when loading the CPU state. Introduce tcg-stub.c just like kvm-stub.c for tcg specific stubs. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/tcg: implement SET CLOCKDavid Hildenbrand4-2/+27
This allows a guest to change its TOD. We already take care of updating all CKC timers from within S390TODClass. Use MO_ALIGN to load the operand manually - this will properly trigger a SPECIFICATION exception. Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/tcg: SET CLOCK COMPARATOR can clear CKC interruptsDavid Hildenbrand1-0/+7
Let's stop the timer and delete any pending CKC IRQ before doing anything else. While at it, add a comment why the check for ckc == -1ULL is needed. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/tcg: properly implement the TODDavid Hildenbrand5-30/+37
Right now, each CPU has its own TOD. Especially, the TOD will differ based on creation time of a CPU - e.g. when hotplugging a CPU the times will differ quite a lot, resulting in stall warnings in the guest. Let's use a single TOD by implementing our new TOD device. Prepare it for TOD-clock epoch extension. Most importantly, whenever we set the TOD, we have to update the CKC timer. Introduce "tcg_s390x.h" just like "kvm_s390x.h" for tcg specific function declarations that should not go into cpu.h. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/tcg: drop tod_basetimeDavid Hildenbrand3-4/+2
Never set to anything but 0. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/tod: factor out TOD into separate deviceDavid Hildenbrand3-34/+2
Let's treat this like a separate device. TCG will have to store the actual state/time later on. Include cpu-qom.h in kvm_s390x.h (due to S390CPU) to compile tod-kvm.c. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/kvm: pass values instead of pointers to kvm_s390_set_clock_*()David Hildenbrand4-12/+12
We are going to factor out the TOD into a separate device and use const pointers for device class functions where possible. We are passing right now ordinary pointers that should never be touched when setting the TOD. Let's just pass the values directly. Note that s390_set_clock() will be removed in a follow-on patch and therefore its calling convention is not changed. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/tcg: avoid overflows in time2tod/tod2timeDavid Hildenbrand1-2/+3
Big values for the TOD/ns clock can result in some overflows that can be avoided. Not all overflows can be handled however, as the conversion either multiplies by 4.096 or divided by 4.096. Apply the trick used in the Linux kernel in arch/s390/include/asm/timex.h for tod_to_ns() and use the same trick also for the conversion in the other direction. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/cpumodel: default enable bpb and ppa15 for z196 and laterChristian Borntraeger1-0/+2
Most systems and host kernels provide the necessary building blocks for bpb and ppa15. We can reverse the logic and default enable those features, while still allowing to disable it via cpu model. So let us add bpb and ppa15 to z196 and later default CPU model for the qemu 3.0 machine. (like -cpu z13). Older machine types (e.g. s390-ccw-virtio-2.12) will retain the old value and not provide those bits in the default model. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20180626123830.18282-1-borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02loader: Check access size when calling rom_ptr() to avoid crashesThomas Huth1-1/+1
The rom_ptr() function allows direct access to the ROM blobs that we load during startup. However, there are currently no checks for the size of the accesses, so it's currently possible to crash QEMU for example with: $ echo "Insane in the mainframe" > /tmp/test.txt $ s390x-softmmu/qemu-system-s390x -kernel /tmp/test.txt -append xyz Segmentation fault (core dumped) $ s390x-softmmu/qemu-system-s390x -kernel /tmp/test.txt -initrd /tmp/test.txt Segmentation fault (core dumped) $ echo -n HdrS > /tmp/hdr.txt $ sparc64-softmmu/qemu-system-sparc64 -kernel /tmp/hdr.txt -initrd /tmp/hdr.txt Segmentation fault (core dumped) We need a possibility to check the size of the ROM area that we want to access, thus let's add a size parameter to the rom_ptr() function to avoid these problems. Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1530005740-25254-1-git-send-email-thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-06-30xtensa: Avoid calling get_page_addr_code() from helper functionPeter Maydell1-1/+5
The xtensa frontend calls get_page_addr_code() from its itlb_hit_test helper function. This function is really part of the TCG core's internals, and calling it from a target helper makes it awkward to make changes to that core code. It also means that we don't pass the correct retaddr to tlb_fill(), so we won't correctly handle the case where an exception is generated. The helper is used for the instructions IHI, IHU and IPFL. Change it to call cpu_ldb_code_ra() instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-30target/xtensa: Convert to TranslatorOpsRichard Henderson1-101/+116
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: Change gen_intermediate_code dc to pointerRichard Henderson1-61/+61
This will reduce the size of the patch in the next patch, where the context will have to be a pointer. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: Convert to DisasContextBaseRichard Henderson1-47/+44
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURNRichard Henderson1-12/+9
The usage of DISAS_UPDATE is after noreturn helpers. It is thus indistinguishable from DISAS_NORETURN. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: check zero overhead loop alignmentMax Filippov3-0/+9
ISA book documents that the first instruction of zero overhead loop must fit completely into naturally aligned region of an instruction fetch unit size. Check that condition and log a message if it's violated. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-29target/arm: Add ID_ISAR6Richard Henderson4-3/+9
This register was added to aa32 state by ARMv8.2. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180629001538.11415-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Prune a15 features from maxRichard Henderson1-3/+0
There is no need to re-set these 3 features already implied by the call to aarch64_a15_initfn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180629001538.11415-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Prune a57 features from maxRichard Henderson1-9/+0
There is no need to re-set these 9 features already implied by the call to aarch64_a57_initfn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180629001538.11415-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Fix SVE system register access checksRichard Henderson2-7/+6
Leave ARM_CP_SVE, removing ARM_CP_FPU; the sve_access_check produced by the flag already includes fp_access_check. If we also check ARM_CP_FPU the double fp_access_check asserts. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180629001538.11415-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Fix SVE signed division vs x86 overflow exceptionRichard Henderson1-5/+15
We already check for the same condition within the normal integer sdiv and sdiv64 helpers. Use a slightly different formation that does not require deducing the expression type. Fixes: f97cfd596ed Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180629001538.11415-2-richard.henderson@linaro.org [PMM: reworded a comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Mark PMINTENSET accesses as possibly doing IOAaron Lindsay1-1/+1
This makes it match its AArch64 equivalent, PMINTENSET_EL1 Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Message-id: 1529699547-17044-13-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Remove redundant DIV detection for KVMAaron Lindsay1-18/+1
KVM implies V7VE, which implies ARM_DIV and THUMB_DIV. The conditional detection here is therefore unnecessary. Because V7VE is already unconditionally specified for all KVM hosts, ARM_DIV and THUMB_DIV are already indirectly specified and do not need to be included here at all. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Message-id: 1529699547-17044-6-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization ExtensionsAaron Lindsay3-11/+19
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Message-id: 1529699547-17044-5-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: support reading of CNT[VCT|FRQ]_EL0 from user-spaceAlex Bennée1-3/+24
Since kernel commit a86bd139f2 (arm64: arch_timer: Enable CNTVCT_EL0 trap..), released in kernel version v4.12, user-space has been able to read these system registers. As we can't use QEMUTimer's in linux-user mode we just directly call cpu_get_clock(). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180625160009.17437-2-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement ARMv8.2-DotProdRichard Henderson5-21/+92
We've already added the helpers with an SVE patch, all that remains is to wire up the aa64 and aa32 translators. Enable the feature within -cpu max for CONFIG_USER_ONLY. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-36-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Enable SVE for aarch64-linux-userRichard Henderson2-0/+8
Enable ARM_FEATURE_SVE for the generic "max" cpu. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-35-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE dot product (indexed)Richard Henderson4-0/+153
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180627043328.11531-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE dot product (vectors)Richard Henderson4-0/+92
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-33-richard.henderson@linaro.org [PMM: moved 'ra=%reg_movprfx' here from following patch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE fp complex multiply add (indexed)Richard Henderson3-20/+59
Enhance the existing helpers to support SVE, which takes the index from each 128-bit segment. The change has no effect for AdvSIMD, since there is only one such segment. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180627043328.11531-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Pass index to AdvSIMD FCMLA (indexed)Richard Henderson3-22/+41
For aa64 advsimd, we had been passing the pre-indexed vector. However, sve applies the index to each 128-bit segment, so we need to pass in the index separately. For aa32 advsimd, the fp32 operation always has index 0, but we failed to interpret the fp16 index correctly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180627043328.11531-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE fp complex multiply addRichard Henderson4-0/+207
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE floating-point complex addRichard Henderson4-0/+135
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE MOVPRFXRichard Henderson2-1/+66
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE floating-point unary operationsRichard Henderson4-0/+52
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE floating-point round to integral valueRichard Henderson4-0/+108
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE floating-point convert to integerRichard Henderson6-7/+211
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE floating-point convert precisionRichard Henderson4-0/+106
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE floating-point trig multiply-add coefficientRichard Henderson4-0/+104
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE FP Compare with Zero GroupRichard Henderson4-0/+138
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Implement SVE Floating Point Unary Operations - Unpredicated GroupRichard Henderson4-0/+80
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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