| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-05-18 | target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing | Peter Maydell | 1 | -2/+9 |
| 2023-05-18 | target/arm: Convert ERET, ERETAA, ERETAB to decodetree | Peter Maydell | 2 | -108/+63 |
| 2023-05-18 | target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree | Peter Maydell | 2 | -58/+43 |
| 2023-05-18 | target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree | Peter Maydell | 2 | -55/+84 |
| 2023-05-18 | target/arm: Convert BR, BLR, RET to decodetree | Peter Maydell | 2 | -6/+54 |
| 2023-05-18 | target/arm: Convert conditional branch insns to decodetree | Peter Maydell | 2 | -24/+8 |
| 2023-05-18 | target/arm: Convert TBZ, TBNZ to decodetree | Peter Maydell | 2 | -20/+11 |
| 2023-05-18 | target/arm: Convert CBZ, CBNZ to decodetree | Peter Maydell | 2 | -20/+11 |
| 2023-05-18 | target/arm: Convert unconditional branch immediate to decodetree | Peter Maydell | 2 | -19/+19 |
| 2023-05-18 | target/arm: Convert Extract instructions to decodetree | Peter Maydell | 2 | -63/+34 |
| 2023-05-18 | target/arm: Convert Bitfield to decodetree | Richard Henderson | 2 | -57/+88 |
| 2023-05-18 | target/arm: Convert Move wide (immediate) to decodetree | Richard Henderson | 2 | -43/+41 |
| 2023-05-18 | target/arm: Convert Logical (immediate) to decodetree | Richard Henderson | 2 | -64/+43 |
| 2023-05-18 | target/arm: Replace bitmask64 with MAKE_64BIT_MASK | Richard Henderson | 1 | -9/+2 |
| 2023-05-18 | target/arm: Convert Add/subtract (immediate with tags) to decodetree | Richard Henderson | 2 | -27/+19 |
| 2023-05-18 | target/arm: Convert Add/subtract (immediate) to decodetree | Richard Henderson | 3 | -53/+42 |
| 2023-05-18 | target/arm: Split gen_add_CC and gen_sub_CC | Richard Henderson | 1 | -60/+79 |
| 2023-05-18 | target/arm: Convert PC-rel addressing to decodetree | Richard Henderson | 2 | -24/+27 |
| 2023-05-18 | target/arm: Pull calls to disas_sve() and disas_sme() out of legacy decoder | Peter Maydell | 1 | -16/+4 |
| 2023-05-18 | target/arm: Create decodetree skeleton for A64 | Peter Maydell | 3 | -7/+32 |
| 2023-05-18 | target/arm: Split out disas_a64_legacy | Richard Henderson | 1 | -38/+44 |
| 2023-05-18 | target/arm: add RAZ/WI handling for DBGDTR[TX|RX] | Alex Bennée | 1 | -2/+9 |
| 2023-05-18 | arm/kvm: add support for MTE | Cornelia Huck | 5 | -4/+68 |
| 2023-05-18 | target/arm: Fix vd == vm overlap in sve_ldff1_z | Richard Henderson | 1 | -0/+6 |
| 2023-05-16 | target/s390x: Fix EXECUTE of relative branches | Ilya Leoshkevich | 1 | -23/+58 |
| 2023-05-16 | s390x/tcg: Fix LDER instruction format | Ilya Leoshkevich | 1 | -1/+1 |
| 2023-05-16 | hw/core: Use a callback for target specific query-cpus-fast information | Thomas Huth | 1 | -0/+8 |
| 2023-05-13 | Merge tag 'or1k-pull-request-20230513' of https://github.com/stffrdhrn/qemu i... | Richard Henderson | 4 | -53/+81 |
| 2023-05-12 | target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check | Peter Maydell | 5 | -19/+30 |
| 2023-05-12 | target/arm: Select CONFIG_ARM_V7M when TCG is enabled | Fabiano Rosas | 1 | -0/+1 |
| 2023-05-12 | target/arm: Select SEMIHOSTING when using TCG | Fabiano Rosas | 1 | -7/+1 |
| 2023-05-12 | target/arm: Fix handling of SW and NSW bits for stage 2 walks | Peter Maydell | 1 | -25/+51 |
| 2023-05-12 | target/arm: Don't allow stage 2 page table walks to downgrade to NS | Peter Maydell | 1 | -2/+3 |
| 2023-05-12 | target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ | Richard Henderson | 5 | -4/+4 |
| 2023-05-12 | target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/ | Richard Henderson | 3 | -0/+0 |
| 2023-05-11 | target/openrisc: Setup FPU for detecting tininess before rounding | Stafford Horne | 1 | -0/+4 |
| 2023-05-11 | target/openrisc: Set PC to cpu state on FPU exception | Stafford Horne | 1 | -2/+11 |
| 2023-05-11 | target/openrisc: Allow fpcsr access in user mode | Stafford Horne | 2 | -51/+66 |
| 2023-05-11 | target/loongarch: Do not include tcg-ldst.h | Richard Henderson | 2 | -2/+0 |
| 2023-05-11 | target/sh4: Use MO_ALIGN where required | Richard Henderson | 1 | -36/+66 |
| 2023-05-11 | target/nios2: Remove TARGET_ALIGNED_ONLY | Richard Henderson | 1 | -0/+10 |
| 2023-05-11 | target/mips: Use MO_ALIGN instead of 0 | Richard Henderson | 1 | -1/+1 |
| 2023-05-11 | target/mips: Add missing default_tcg_memop_mask | Richard Henderson | 4 | -28/+42 |
| 2023-05-11 | target/mips: Add MO_ALIGN to gen_llwp, gen_scwp | Richard Henderson | 1 | -2/+3 |
| 2023-05-11 | target/m68k: Fix gen_load_fp for OS_LONG | Richard Henderson | 1 | -0/+1 |
| 2023-05-10 | target/loongarch: Terminate vmstate subsections list | Richard Henderson | 1 | -0/+1 |
| 2023-05-08 | target/i386: Add EPYC-Genoa model to support Zen 4 processor series | Babu Moger | 1 | -0/+122 |
| 2023-05-08 | target/i386: Add VNMI and automatic IBRS feature bits | Babu Moger | 2 | -2/+5 |
| 2023-05-08 | target/i386: Add missing feature bits in EPYC-Milan model | Babu Moger | 1 | -0/+70 |
| 2023-05-08 | target/i386: Add feature bits for CPUID_Fn80000021_EAX | Babu Moger | 2 | -0/+32 |
