| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-03-05 | kvm: add kvm_arm_get_max_vm_ipa_size | Eric Auger | 2 | -0/+23 |
| 2019-03-05 | target/arm: Implement ARMv8.5-FRINT | Richard Henderson | 5 | -5/+173 |
| 2019-03-05 | target/arm: Restructure handle_fp_1src_{single, double} | Richard Henderson | 1 | -41/+49 |
| 2019-03-05 | target/arm: Implement ARMv8.5-CondM | Richard Henderson | 3 | -1/+64 |
| 2019-03-05 | target/arm: Implement ARMv8.4-CondM | Richard Henderson | 3 | -1/+104 |
| 2019-03-05 | target/arm: Rearrange disas_data_proc_reg | Richard Henderson | 1 | -41/+57 |
| 2019-03-05 | target/arm: Add set/clear_pstate_bits, share gen_ss_advance | Richard Henderson | 5 | -29/+34 |
| 2019-03-05 | target/arm: Split helper_msr_i_pstate into 3 | Richard Henderson | 6 | -56/+70 |
| 2019-03-05 | target/arm: Implement ARMv8.0-PredInv | Richard Henderson | 4 | -1/+70 |
| 2019-03-05 | target/arm: Implement ARMv8.0-SB | Richard Henderson | 5 | -0/+49 |
| 2019-03-05 | target/arm: Split out arm_sctlr | Richard Henderson | 2 | -15/+17 |
| 2019-03-05 | target/arm: Fix PC test for LDM (exception return) | Richard Henderson | 1 | -1/+1 |
| 2019-03-04 | s390x: Add floating-point extension facility to "qemu" cpu model | David Hildenbrand | 1 | -0/+5 |
| 2019-03-04 | s390x/tcg: Handle all rounding modes overwritten by BFP instructions | David Hildenbrand | 1 | -2/+11 |
| 2019-03-04 | s390x/tcg: Implement rounding mode and XxC for LOAD ROUNDED | David Hildenbrand | 4 | -15/+44 |
| 2019-03-04 | s390x/tcg: Implement XxC and checks for most FP instructions | David Hildenbrand | 2 | -126/+247 |
| 2019-03-04 | s390x/tcg: Prepare for IEEE-inexact-exception control (XxC) | David Hildenbrand | 1 | -57/+57 |
| 2019-03-04 | s390x/tcg: Refactor saving/restoring the bfp rounding mode | David Hildenbrand | 2 | -43/+71 |
| 2019-03-04 | s390x/tcg: Check for exceptions in SET BFP ROUNDING MODE | David Hildenbrand | 4 | -35/+39 |
| 2019-03-04 | s390x/tcg: Handle SET FPC AND LOAD FPC 3-bit BFP rounding modes | David Hildenbrand | 2 | -5/+19 |
| 2019-03-04 | s390x/tcg: Fix simulated-IEEE exceptions | David Hildenbrand | 1 | -0/+13 |
| 2019-03-04 | s390x/tcg: Refactor SET FPC AND SIGNAL handling | David Hildenbrand | 1 | -10/+12 |
| 2019-03-04 | s390x/tcg: Hide IEEE underflows in some scenarios | David Hildenbrand | 1 | -0/+13 |
| 2019-03-04 | s390x/tcg: Fix parts of IEEE exception handling | David Hildenbrand | 1 | -6/+32 |
| 2019-03-04 | s390x/tcg: Factor out conversion of softfloat exceptions | David Hildenbrand | 2 | -12/+20 |
| 2019-03-04 | s390x/tcg: Fix rounding from float128 to uint64_t/uint32_t | David Hildenbrand | 1 | -6/+2 |
| 2019-03-04 | s390x/tcg: Fix TEST DATA CLASS instructions | David Hildenbrand | 1 | -50/+35 |
| 2019-03-04 | s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARY | David Hildenbrand | 5 | -0/+31 |
| 2019-03-04 | s390x/tcg: Implement LOAD LENGTHENED short HFP to long HFP | David Hildenbrand | 2 | -0/+8 |
| 2019-03-04 | s390x/tcg: Factor out gen_addi_and_wrap_i64() from get_address() | David Hildenbrand | 1 | -15/+26 |
| 2019-03-04 | s390x/tcg: Factor out vec_full_reg_offset() | David Hildenbrand | 1 | -2/+7 |
| 2019-03-04 | s390x/tcg: Clarify terminology in vec_reg_offset() | David Hildenbrand | 1 | -5/+6 |
| 2019-03-04 | s390x/tcg: Simplify disassembler operands initialization | David Hildenbrand | 1 | -7/+1 |
| 2019-03-04 | s390x/tcg: RXE has an optional M3 field | David Hildenbrand | 1 | -1/+1 |
| 2019-03-04 | s390x/tcg: Save vregs to extended mchk save area | David Hildenbrand | 2 | -3/+47 |
| 2019-03-04 | s390x: use a QEMU-style typedef + name for SIGP save area struct | David Hildenbrand | 1 | -4/+4 |
| 2019-03-04 | s390x: Use cpu_to_be64 in SIGP STORE ADDITIONAL STATUS | David Hildenbrand | 1 | -10/+21 |
| 2019-02-28 | Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into staging | Peter Maydell | 8 | -1745/+1855 |
| 2019-02-28 | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190228-... | Peter Maydell | 13 | -103/+519 |
| 2019-02-28 | Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-27-2019' ... | Peter Maydell | 1 | -2/+41 |
| 2019-02-28 | target/xtensa: implement PREFCTL SR | Max Filippov | 2 | -0/+17 |
| 2019-02-28 | target/xtensa: prioritize load/store in FLIX bundles | Max Filippov | 2 | -5/+36 |
| 2019-02-28 | target/xtensa: break circular register dependencies | Max Filippov | 1 | -4/+123 |
| 2019-02-28 | target/xtensa: reorganize access to boolean registers | Max Filippov | 1 | -8/+42 |
| 2019-02-28 | target/xtensa: reorganize access to MAC16 registers | Max Filippov | 1 | -94/+92 |
| 2019-02-28 | target/xtensa: reorganize register handling in translators | Max Filippov | 3 | -344/+386 |
| 2019-02-28 | target/xtensa: only rotate window in the retw helper | Max Filippov | 3 | -9/+10 |
| 2019-02-28 | target/xtensa: move WINDOW_BASE SR update to postprocessing | Max Filippov | 4 | -20/+28 |
| 2019-02-28 | target/xtensa: add generic instruction post-processing | Max Filippov | 2 | -8/+33 |
| 2019-02-28 | target/xtensa: sort FLIX instruction opcodes | Max Filippov | 2 | -8/+221 |
