riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-07-24	target/s390x: Fix assertion failure in VFMIN/VFMAX with type 13	Ilya Leoshkevich	1	-1/+1
2023-07-24	target/s390x: Make MC raise specification exception when class >= 16	Ilya Leoshkevich	2	-3/+3
2023-07-24	target/s390x: Fix ICM with M3=0	Ilya Leoshkevich	1	-0/+6
2023-07-24	target/s390x: Fix CONVERT TO LOGICAL/FIXED with out-of-range inputs	Ilya Leoshkevich	1	-1/+2
2023-07-24	target/s390x: Fix CLM with M3=0	Ilya Leoshkevich	1	-0/+5
2023-07-24	target/s390x: Make CKSM raise an exception if R2 is odd	Ilya Leoshkevich	2	-1/+7
2023-07-19	target/riscv: Fix LMUL check to use VLEN	Rob Bradford	1	-2/+2
2023-07-19	target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf	Daniel Henrique Barboza	1	-1/+2
2023-07-17	target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits	Peter Maydell	1	-5/+8
2023-07-17	target/arm: Fix S1_ptw_translate() debug path	Peter Maydell	1	-5/+32
2023-07-17	target/arm/ptw.c: Add comments to S1Translate struct fields	Peter Maydell	1	-0/+40
2023-07-15	accel/tcg: Return bool from page_check_range	Richard Henderson	3	-3/+3
2023-07-11	Merge tag 'mips-20230710' of https://github.com/philmd/qemu into staging	Richard Henderson	16	-132/+3962
2023-07-10	target/mips: enable GINVx support for I6400 and I6500	Marcin Nowakowski	1	-2/+2
2023-07-10	target/mips/mxu: Add Q8SAD instruction	Siarhei Volkau	1	-0/+45
2023-07-10	target/mips/mxu: Add S32SFL instruction	Siarhei Volkau	1	-0/+81
2023-07-10	target/mips/mxu: Add Q8MADL instruction	Siarhei Volkau	1	-0/+75
2023-07-10	target/mips/mxu: Add Q16SCOP instruction	Siarhei Volkau	1	-0/+85
2023-07-10	target/mips/mxu: Add Q8MAC Q8MACSU instructions	Siarhei Volkau	1	-42/+86
2023-07-10	target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions	Siarhei Volkau	1	-0/+188
2023-07-10	target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions	Siarhei Volkau	1	-4/+162
2023-07-10	target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions	Siarhei Volkau	1	-0/+78
2023-07-10	target/mips/mxu: Add D32SLL D32SLR D32SAR instructions	Siarhei Volkau	1	-0/+55
2023-07-10	target/mips/mxu: Add D32SARL D32SARW instructions	Siarhei Volkau	1	-0/+59
2023-07-10	target/mips/mxu: Add S32ALN S32LUI insns	Siarhei Volkau	1	-1/+121
2023-07-10	target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns	Siarhei Volkau	1	-4/+196
2023-07-10	target/mips/mxu: Add S16LDD S16STD S16LDI S16SDI instructions	Siarhei Volkau	1	-0/+117
2023-07-10	target/mips/mxu: Add S8STD S8LDI S8SDI instructions	Siarhei Volkau	1	-2/+72
2023-07-10	target/mips/mxu: Add Q8ADDE Q8ACCE D8SUM D8SUMC instructions	Siarhei Volkau	1	-0/+200
2023-07-10	target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructions	Siarhei Volkau	1	-1/+227
2023-07-10	target/mips/mxu: Add D32ADDC instruction	Siarhei Volkau	1	-7/+32
2023-07-10	target/mips/mxu: Add D32ACC D32ACCM D32ASUM instructions	Siarhei Volkau	1	-0/+160
2023-07-10	target/mips/mxu: Add D32ADD instruction	Siarhei Volkau	1	-0/+64
2023-07-10	target/mips/mxu: Add Q16ADD instruction	Siarhei Volkau	1	-0/+89
2023-07-10	target/mips/mxu: Add S16MAD instruction	Siarhei Volkau	1	-0/+65
2023-07-10	target/mips/mxu: Add D16MADL instruction	Siarhei Volkau	1	-0/+82
2023-07-10	target/mips/mxu: Add D16MACF D16MACE instructions	Siarhei Volkau	1	-6/+68
2023-07-10	target/mips/mxu: Add D16MULF D16MULE instructions	Siarhei Volkau	1	-5/+90
2023-07-10	target/mips/mxu: Add S32CPS D16CPS Q8ABD Q16SAT insns	Siarhei Volkau	1	-3/+293
2023-07-10	target/mips/mxu: Add Q8ADD instruction	Siarhei Volkau	1	-0/+77
2023-07-10	target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insns	Siarhei Volkau	1	-1/+243
2023-07-10	target/mips/mxu: Fix D16MAX D16MIN Q8MAX Q8MIN instructions	Siarhei Volkau	1	-12/+18
2023-07-10	target/mips/mxu: Add Q8SLT Q8SLTU instructions	Siarhei Volkau	1	-0/+65
2023-07-10	target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructions	Siarhei Volkau	2	-7/+105
2023-07-10	target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructions	Siarhei Volkau	1	-1/+82
2023-07-10	target/mips: Add support of two XBurst CPUs	Siarhei Volkau	1	-0/+46
2023-07-10	target/mips: Add emulation of MXU instructions for 32-bit load/store	Siarhei Volkau	1	-23/+279
2023-07-10	target/mips: Implement Loongson CSR instructions	Jiaxun Yang	14	-0/+238
2023-07-10	Merge tag 'pull-riscv-to-apply-20230710-1' of https://github.com/alistair23/q...	Richard Henderson	16	-128/+1966
2023-07-10	target/mips: Rework cp0_timer with clock API	Jiaxun Yang	3	-20/+26