| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-11-29 | target/ppc: fix Hash64 MMU update of PTE bit R | Leandro Lupori | 2 | -2/+7 |
| 2021-11-22 | Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2" | Peter Maydell | 1 | -6/+29 |
| 2021-11-19 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging | Richard Henderson | 1 | -0/+10 |
| 2021-11-19 | nvmm: Fix support for stable version | nia | 1 | -0/+10 |
| 2021-11-18 | target/i386/sev: Replace qemu_map_ram_ptr with address_space_map | Dov Murik | 1 | -3/+15 |
| 2021-11-18 | target/i386/sev: Perform padding calculations at compile-time | Dov Murik | 1 | -10/+18 |
| 2021-11-18 | target/i386/sev: Fail when invalid hashes table area detected | Dov Murik | 1 | -2/+6 |
| 2021-11-18 | target/i386/sev: Rephrase error message when no hashes table in guest firmware | Dov Murik | 1 | -1/+2 |
| 2021-11-18 | target/i386/sev: Add kernel hashes only if sev-guest.kernel-hashes=on | Dov Murik | 1 | -0/+8 |
| 2021-11-18 | qapi/qom,target/i386: sev-guest: Introduce kernel-hashes=on|off option | Dov Murik | 1 | -0/+20 |
| 2021-11-17 | Merge tag 'pull-request-2021-11-17' of https://gitlab.com/thuth/qemu into sta... | Richard Henderson | 1 | -5/+0 |
| 2021-11-17 | target/riscv: machine: Sort the .subsections | Bin Meng | 1 | -46/+46 |
| 2021-11-17 | target/s390x/cpu.h: Remove unused SIGP_MODE defines | Thomas Huth | 1 | -5/+0 |
| 2021-11-11 | ppc/mmu_helper.c: do not truncate 'ea' in booke206_invalidate_ea_tlb() | Daniel Henrique Barboza | 1 | -1/+1 |
| 2021-11-10 | target/ppc: Fix register update on lf[sd]u[x]/stf[sd]u[x] | Matheus Ferst | 1 | -1/+1 |
| 2021-11-09 | target/ppc: cntlzdm/cnttzdm implementation without brcond | Matheus Ferst | 1 | -15/+16 |
| 2021-11-09 | target/ppc: Implement lxvkq instruction | Matheus Ferst | 2 | -0/+50 |
| 2021-11-09 | target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions | Matheus Ferst | 4 | -0/+93 |
| 2021-11-09 | target/ppc: implemented XXSPLTIDP instruction | Bruno Larsen (billionai) | 2 | -0/+12 |
| 2021-11-09 | target/ppc: Implemented XXSPLTIW using decodetree | Bruno Larsen (billionai) | 2 | -0/+16 |
| 2021-11-09 | target/ppc: implemented XXSPLTI32DX | Bruno Larsen (billionai) | 2 | -0/+28 |
| 2021-11-09 | target/ppc: moved XXSPLTIB to using decodetree | Bruno Larsen (billionai) | 3 | -15/+11 |
| 2021-11-09 | target/ppc: moved XXSPLTW to using decodetree | Bruno Larsen (billionai) | 3 | -12/+15 |
| 2021-11-09 | target/ppc: added the instructions PLXVP and PSTXVP | Lucas Mateus Castro (alqotel) | 2 | -0/+11 |
| 2021-11-09 | target/ppc: added the instructions PLXV and PSTXV | Lucas Mateus Castro (alqotel) | 2 | -0/+26 |
| 2021-11-09 | target/ppc: added the instructions LXVPX and STXVPX | Lucas Mateus Castro (alqotel) | 2 | -6/+15 |
| 2021-11-09 | target/ppc: added the instructions LXVP and STXVP | Lucas Mateus Castro (alqotel) | 2 | -12/+48 |
| 2021-11-09 | target/ppc: moved stxvx and lxvx from legacy to decodtree | Lucas Mateus Castro (alqotel) | 3 | -108/+20 |
| 2021-11-09 | target/ppc: moved stxv and lxv from legacy to decodtree | Lucas Mateus Castro (alqotel) | 3 | -17/+59 |
| 2021-11-09 | target/ppc: receive high/low as argument in get/set_cpu_vsr | Matheus Ferst | 1 | -171/+146 |
| 2021-11-09 | target/ppc: Introduce REQUIRE_VSX macro | Bruno Larsen (billionai) | 1 | -0/+8 |
| 2021-11-09 | target/ppc: Implement Vector Extract Double to VSR using GPR index insns | Matheus Ferst | 4 | -0/+92 |
| 2021-11-09 | target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree | Matheus Ferst | 5 | -42/+30 |
| 2021-11-09 | target/ppc: Implement Vector Insert from VSR using GPR index insns | Matheus Ferst | 2 | -0/+39 |
| 2021-11-09 | target/ppc: Implement Vector Insert Word from GPR using Immediate insns | Matheus Ferst | 2 | -0/+43 |
| 2021-11-09 | target/ppc: Implement Vector Insert from GPR using GPR index insns | Matheus Ferst | 4 | -0/+93 |
| 2021-11-09 | target/ppc: Implement vsldbi/vsrdbi instructions | Matheus Ferst | 2 | -0/+74 |
| 2021-11-09 | target/ppc: Implement vpdepd/vpextd instruction | Matheus Ferst | 4 | -3/+35 |
| 2021-11-09 | target/ppc: Implement vclzdm/vctzdm instructions | Matheus Ferst | 3 | -3/+35 |
| 2021-11-09 | target/ppc: Move vcfuged to vmx-impl.c.inc | Matheus Ferst | 6 | -52/+19 |
| 2021-11-09 | target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree | Luis Pires | 6 | -87/+68 |
| 2021-11-09 | target/ppc: Move dct{dp,qpq},dr{sp,dpq},dc{f,t}fix[q],dxex[q] to decodetree | Luis Pires | 5 | -70/+69 |
| 2021-11-09 | target/ppc: Move dqua[q], drrnd[q] to decodetree | Luis Pires | 5 | -62/+47 |
| 2021-11-09 | target/ppc: Move dquai[q], drint{x,n}[q] to decodetree | Luis Pires | 5 | -58/+58 |
| 2021-11-09 | target/ppc: Move dcmp{u,o}[q],dts{tex,tsf,tsfi}[q] to decodetree | Luis Pires | 5 | -91/+83 |
| 2021-11-09 | target/ppc: Move d{add,sub,mul,div,iex}[q] to decodetree | Luis Pires | 5 | -70/+76 |
| 2021-11-09 | target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree | Luis Pires | 5 | -38/+37 |
| 2021-11-09 | target/ppc: Do not update nip on DFP instructions | Luis Pires | 1 | -8/+0 |
| 2021-11-09 | target/ppc: Implement DCTFIXQQ | Luis Pires | 4 | -0/+75 |
| 2021-11-09 | target/ppc: Implement DCFFIXQQ | Luis Pires | 5 | -0/+43 |
