riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-06-17	Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...	Peter Maydell	4	-50/+94
2021-06-16	bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations	Peter Maydell	1	-20/+0
2021-06-16	target/arm: Move expand_pred_b() data to vec_helper.c	Peter Maydell	3	-99/+109
2021-06-16	target/arm: Add framework for MVE decode	Peter Maydell	5	-0/+53
2021-06-16	target/arm: Implement MVE LETP insn	Peter Maydell	2	-9/+97
2021-06-16	target/arm: Implement MVE DLSTP	Peter Maydell	2	-5/+27
2021-06-16	target/arm: Implement MVE WLSTP insn	Peter Maydell	2	-3/+42
2021-06-16	target/arm: Implement MVE LCTP	Peter Maydell	2	-0/+26
2021-06-16	target/arm: Let vfp_access_check() handle late NOCP checks	Peter Maydell	1	-5/+15
2021-06-16	target/arm: Add handling for PSR.ECI/ICI	Peter Maydell	5	-5/+133
2021-06-16	target/arm: Handle VPR semantics in existing code	Peter Maydell	3	-11/+57
2021-06-16	target/arm: Enable FPSCR.QC bit for MVE	Peter Maydell	2	-10/+23
2021-06-16	target/arm: Provide and use H8 and H1_8 macros	Peter Maydell	3	-137/+143
2021-06-16	target/arm: Fix mte page crossing test	Richard Henderson	1	-1/+1
2021-06-16	target/i386: Added Intercept CR0 writes check	Lara Lazier	1	-0/+9
2021-06-16	target/i386: Added consistency checks for CR0	Lara Lazier	3	-3/+13
2021-06-16	target/i386: Added consistency checks for VMRUN intercept and ASID	Lara Lazier	1	-0/+10
2021-06-16	target/i386: Refactored intercept checks into cpu_svm_has_intercept	Lara Lazier	2	-47/+62
2021-06-15	target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16	Richard Henderson	1	-30/+48
2021-06-15	target/arm: Remove fprintf from disas_simd_mod_imm	Richard Henderson	1	-1/+0
2021-06-15	target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16	Richard Henderson	1	-2/+2
2021-06-08	Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...	Peter Maydell	13	-104/+1028
2021-06-08	target/riscv: rvb: add b-ext version cpu option	Frank Chang	2	-0/+26
2021-06-08	target/riscv: rvb: support and turn on B-extension from command line	Kito Cheng	2	-0/+5
2021-06-08	target/riscv: rvb: add/shift with prefix zero-extend	Kito Cheng	3	-0/+35
2021-06-08	target/riscv: rvb: address calculation	Kito Cheng	3	-0/+62
2021-06-08	target/riscv: rvb: generalized or-combine	Frank Chang	5	-0/+64
2021-06-08	target/riscv: rvb: generalized reverse	Frank Chang	6	-0/+132
2021-06-08	target/riscv: rvb: rotate (left/right)	Kito Cheng	3	-0/+81
2021-06-08	target/riscv: rvb: shift ones	Kito Cheng	3	-0/+74
2021-06-08	target/riscv: rvb: single-bit instructions	Frank Chang	3	-0/+175
2021-06-08	target/riscv: add gen_shifti() and gen_shiftiw() helper functions	Frank Chang	2	-50/+43
2021-06-08	target/riscv: rvb: sign-extend instructions	Kito Cheng	2	-0/+15
2021-06-08	target/riscv: rvb: min/max instructions	Kito Cheng	2	-0/+28
2021-06-08	target/riscv: rvb: pack two words into one register	Kito Cheng	3	-0/+78
2021-06-08	target/riscv: rvb: logic-with-negate	Kito Cheng	2	-0/+21
2021-06-08	target/riscv: rvb: count bits set	Frank Chang	3	-0/+21
2021-06-08	target/riscv: rvb: count leading/trailing zeros	Kito Cheng	4	-1/+93
2021-06-08	target/riscv: reformat @sh format encoding for B-extension	Kito Cheng	1	-5/+5
2021-06-08	target/riscv: Pass the same value to oprsz and maxsz.	LIU Zhiwei	1	-39/+50
2021-06-08	target/riscv/pmp: Add assert for ePMP operations	Alistair Francis	1	-0/+4
2021-06-08	target/riscv: Dump CSR mscratch/sscratch/satp	Changbin Du	1	-2/+5
2021-06-08	target/riscv: Remove unnecessary riscv_*_names[] declaration	Bin Meng	2	-4/+2
2021-06-08	target/riscv: Do not include 'pmp.h' in user emulation	Philippe Mathieu-Daudé	1	-0/+2
2021-06-08	target/riscv: fix wfi exception behavior	Jose Martins	2	-3/+9
2021-06-05	target/mips: Fix 'Uncoditional' typo	Philippe Mathieu-Daudé	1	-3/+3
2021-06-05	target/hppa: Remove unused 'memory.h' header	Philippe Mathieu-Daudé	1	-1/+0
2021-06-05	target/nios2: fix page-fit instruction count	Pavel Dovgalyuk	1	-1/+1
2021-06-05	target/riscv: Do not include 'pmp.h' in user emulation	Philippe Mathieu-Daudé	1	-0/+2
2021-06-04	i386: run accel_cpu_instance_init as post_init	Claudio Fontana	1	-3/+7