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2021-04-17target/arm: drop CF_LAST_IO/dc->condjump checkAlex Bennée1-5/+0
2021-04-13target/mips: Fix TCG temporary leak in gen_cache_operation()Philippe Mathieu-Daudé1-0/+2
2021-04-12target/arm: Check PAGE_WRITE_ORG for MTE writeabilityRichard Henderson1-1/+1
2021-04-09i386: Add missing cpu feature bits in EPYC-Rome modelBabu Moger1-0/+12
2021-04-06Revert "target/arm: Make number of counters in PMCR follow the CPU"Peter Maydell5-28/+12
2021-04-05target/alpha: fix icount handling for timer instructionsPavel Dovgalyuk1-2/+7
2021-04-04Merge remote-tracking branch 'remotes/xtensa/tags/20210403-xtensa' into stagingPeter Maydell2-12/+5
2021-04-03target/xtensa: make xtensa_modules static on importMax Filippov1-0/+1
2021-04-03target/xtensa: fix meson.build rule for xtensa coresMax Filippov2-12/+4
2021-04-01hexagon: do not specify Python scripts as inputsPaolo Bonzini1-20/+10
2021-04-01hexagon: do not specify executables as inputsPaolo Bonzini1-4/+2
2021-04-01target/openrisc: fix icount handling for timer instructionsPavel Dovgalyuk1-0/+15
2021-04-01target/i386: Verify memory operand for lcall and ljmpRichard Henderson1-0/+6
2021-03-31target/ppc/kvm: Cache timebase frequencyGreg Kurz1-6/+19
2021-03-30target/arm: Make number of counters in PMCR follow the CPUPeter Maydell5-12/+28
2021-03-26s390x: move S390_ADAPTER_SUPPRESSIBLEGerd Hoffmann1-3/+6
2021-03-23Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210323'...Peter Maydell2-1/+2
2021-03-23target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fillRichard Henderson1-0/+1
2021-03-23target/arm: Make M-profile VTOR loads on reset handle memory aliasingPeter Maydell1-1/+1
2021-03-22target/riscv: Prevent lost illegal instruction exceptionsGeorg Kotheimer1-178/+1
2021-03-22target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer3-13/+13
2021-03-22target/riscv: Fix read and write accesses to vsip and vsieGeorg Kotheimer1-34/+34
2021-03-22target/riscv: Use background registers also for MSTATUS_MPVGeorg Kotheimer1-1/+1
2021-03-22target/riscv: Make VSTIP and VSEIP read-only in hipGeorg Kotheimer1-3/+4
2021-03-22target/riscv: Adjust privilege level for HLV(X)/HSV instructionsGeorg Kotheimer1-11/+14
2021-03-22target/riscv: flush TLB pages if PMP permission has been changedJim Shu1-0/+4
2021-03-22target/riscv: add log of PMP permission checkingJim Shu1-0/+12
2021-03-22target/riscv: propagate PMP permission to TLB pageJim Shu3-43/+125
2021-03-22target/riscv: fix vs() to return proper error codeFrank Chang1-1/+1
2021-03-22target/mips/mxu_translate.c: Fix array overrun for D16MIN/D16MAXPeter Maydell1-4/+4
2021-03-19i386: Make migration fail when Hyper-V reenlightenment was enabled but 'user_...Vitaly Kuznetsov2-0/+21
2021-03-19i386: Fix 'hypercall_hypercall' typoVitaly Kuznetsov1-2/+2
2021-03-19target/i386: svm: do not discard high 32 bits of EXITINFO1Paolo Bonzini3-11/+10
2021-03-19target/i386: fail if toggling LA57 in 64-bit modePaolo Bonzini1-0/+4
2021-03-19target/i386: allow modifying TCG phys-addr-bitsPaolo Bonzini4-27/+16
2021-03-17Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210316' into...Peter Maydell8-73/+153
2021-03-15Merge remote-tracking branch 'remotes/philmd/tags/avr-20210315' into stagingPeter Maydell1-4/+6
2021-03-15Merge remote-tracking branch 'remotes/bkoppelmann2/tags/pull-tricore-20210314...Peter Maydell3-22/+20
2021-03-15target/s390x: Store r1/r2 for page-translation exceptions during MVPGDavid Hildenbrand4-21/+36
2021-03-15target/s390x: Implement the MVPG condition-code-option bitRichard Henderson3-23/+121
2021-03-15s390x/cpu_model: use official name for 8562Cornelia Huck1-2/+2
2021-03-15s390x/kvm: Get rid of legacy_s390_alloc()David Hildenbrand1-38/+5
2021-03-15target/avr: Fix interrupt executionIvanov Arkasha1-1/+3
2021-03-15target/avr: Fix some comment spelling errorsLichang Zhao1-3/+3
2021-03-14Merge remote-tracking branch 'remotes/philmd/tags/mips-20210313' into stagingPeter Maydell7-3645/+2017
2021-03-14target/tricore: Fix OPC2_32_RRPW_EXTR for width=0Bastian Koppelmann1-0/+5
2021-03-14target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2Bastian Koppelmann1-1/+7
2021-03-14tricore: fixed faulty conditions for extr and imaskAndreas Konopik1-4/+4
2021-03-14target/tricore: Remove unused definitionsPhilippe Mathieu-Daudé1-12/+0
2021-03-14target/tricore: Pass MMUAccessType to get_physical_address()Philippe Mathieu-Daudé1-4/+2