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Author
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Lines
2020-07-10
qom: Use returned bool to check for failure, Coccinelle part
Markus Armbruster
3
-11
/
+6
2020-07-10
qom: Put name parameter before value / visitor parameter
Markus Armbruster
4
-33
/
+30
2020-07-10
qapi: Use returned bool to check for failure, Coccinelle part
Markus Armbruster
6
-28
/
+14
2020-07-08
Merge remote-tracking branch 'remotes/vivier/tags/m68k-next-pull-request' int...
Peter Maydell
1
-9
/
+8
2020-07-07
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
Peter Maydell
1
-0
/
+7
2020-07-06
target/m68k: consolidate physical translation offset into get_physical_address()
Mark Cave-Ayland
1
-11
/
+6
2020-07-06
target/m68k: fix physical address translation in m68k_cpu_get_phys_page_debug()
Mark Cave-Ayland
1
-0
/
+4
2020-07-06
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...
Peter Maydell
1
-0
/
+2
2020-07-04
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200703'...
Peter Maydell
8
-6
/
+184
2020-07-04
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200703' into staging
Peter Maydell
1
-1
/
+1
2020-07-03
target/arm: Fix temp double-free in sve ldr/str
Richard Henderson
3
-6
/
+9
2020-07-03
target/arm: kvm: Handle misconfigured dabt injection
Beata Michalska
5
-1
/
+124
2020-07-03
target/arm: kvm: Handle DABT with no valid ISS
Beata Michalska
1
-0
/
+52
2020-07-03
target/s390x: Fix SQXBR
Richard Henderson
1
-1
/
+1
2020-07-02
target/riscv: configure and turn on vector extension from command line
LIU Zhiwei
2
-1
/
+46
2020-07-02
target/riscv: vector compress instruction
LIU Zhiwei
4
-0
/
+64
2020-07-02
target/riscv: vector register gather instruction
LIU Zhiwei
4
-0
/
+150
2020-07-02
target/riscv: vector slide instructions
LIU Zhiwei
4
-0
/
+155
2020-07-02
target/riscv: floating-point scalar move instructions
LIU Zhiwei
2
-0
/
+52
2020-07-02
target/riscv: integer scalar move instruction
LIU Zhiwei
3
-0
/
+67
2020-07-02
target/riscv: integer extract instruction
LIU Zhiwei
2
-0
/
+117
2020-07-02
target/riscv: vector element index instruction
LIU Zhiwei
4
-0
/
+56
2020-07-02
target/riscv: vector iota instruction
LIU Zhiwei
4
-0
/
+62
2020-07-02
target/riscv: set-X-first mask bit
LIU Zhiwei
4
-0
/
+98
2020-07-02
target/riscv: vmfirst find-first-set mask bit
LIU Zhiwei
4
-0
/
+54
2020-07-02
target/riscv: vector mask population count vmpopc
LIU Zhiwei
4
-0
/
+55
2020-07-02
target/riscv: vector mask-register logical instructions
LIU Zhiwei
4
-0
/
+92
2020-07-02
target/riscv: vector widening floating-point reduction instructions
LIU Zhiwei
4
-0
/
+54
2020-07-02
target/riscv: vector single-width floating-point reduction instructions
LIU Zhiwei
4
-0
/
+58
2020-07-02
target/riscv: vector wideing integer reduction instructions
LIU Zhiwei
4
-0
/
+24
2020-07-02
target/riscv: vector single-width integer reduction instructions
LIU Zhiwei
4
-0
/
+133
2020-07-02
target/riscv: narrowing floating-point/integer type-convert instructions
LIU Zhiwei
4
-0
/
+103
2020-07-02
target/riscv: widening floating-point/integer type-convert instructions
LIU Zhiwei
4
-0
/
+106
2020-07-02
target/riscv: vector floating-point/integer type-convert instructions
LIU Zhiwei
4
-0
/
+56
2020-07-02
target/riscv: vector floating-point merge instructions
LIU Zhiwei
4
-0
/
+68
2020-07-02
target/riscv: vector floating-point classify instructions
LIU Zhiwei
6
-30
/
+107
2020-07-02
target/riscv: vector floating-point compare instructions
LIU Zhiwei
4
-0
/
+258
2020-07-02
target/riscv: vector floating-point sign-injection instructions
LIU Zhiwei
4
-0
/
+118
2020-07-02
target/riscv: vector floating-point min/max instructions
LIU Zhiwei
4
-0
/
+50
2020-07-02
target/riscv: vector floating-point square-root instruction
LIU Zhiwei
4
-0
/
+93
2020-07-02
target/riscv: vector widening floating-point fused multiply-add instructions
LIU Zhiwei
4
-0
/
+126
2020-07-02
target/riscv: vector single-width floating-point fused multiply-add instructions
LIU Zhiwei
4
-0
/
+334
2020-07-02
target/riscv: vector widening floating-point multiply
LIU Zhiwei
4
-0
/
+33
2020-07-02
target/riscv: vector single-width floating-point multiply/divide instructions
LIU Zhiwei
4
-0
/
+77
2020-07-02
target/riscv: vector widening floating-point add/subtract instructions
LIU Zhiwei
4
-0
/
+257
2020-07-02
target/riscv: vector single-width floating-point add/subtract instructions
LIU Zhiwei
4
-0
/
+250
2020-07-02
target/riscv: vector narrowing fixed-point clip instructions
LIU Zhiwei
4
-0
/
+168
2020-07-02
target/riscv: vector single-width scaling shift instructions
LIU Zhiwei
4
-0
/
+148
2020-07-02
target/riscv: vector widening saturating scaled multiply-add
LIU Zhiwei
4
-0
/
+243
2020-07-02
target/riscv: vector single-width fractional multiply with rounding and satur...
LIU Zhiwei
4
-0
/
+122
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