riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-04-18	s390x/kvm: Report warnings with warn_report(), not error_printf()	Markus Armbruster	1	-1/+1
2019-04-09	target/i386: Generate #UD for LOCK on a register increment	Peter Maydell	1	-0/+5
2019-03-29	target/ppc: Fix QEMU crash with stxsdx	Greg Kurz	1	-1/+1
2019-03-29	target/ppc: Improve comment of bcctr used for spectre v2 mitigation	Greg Kurz	1	-1/+9
2019-03-29	target/ppc: Consolidate 64-bit server processor detection in a helper	Greg Kurz	3	-7/+11
2019-03-29	target/ppc: Enable "decrement and test CTR" version of bcctr	Greg Kurz	1	-15/+37
2019-03-29	target/ppc: Fix TCG temporary leaks in gen_bcond()	Greg Kurz	1	-0/+2
2019-03-28	Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging	Peter Maydell	1	-0/+11
2019-03-28	Merge remote-tracking branch 'remotes/xtensa/tags/20190326-xtensa' into staging	Peter Maydell	2	-2/+0
2019-03-26	target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu max	Richard Henderson	1	-0/+5
2019-03-26	target/riscv: Fix wrong expanding for c.fswsp	Kito Cheng	1	-1/+1
2019-03-26	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-rc1' i...	Peter Maydell	2	-2/+23
2019-03-25	Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' int...	Peter Maydell	7	-17/+17
2019-03-25	target/arm: make pmccntr_op_start/finish static	Andrew Jones	2	-13/+2
2019-03-25	target/arm: cortex-a7 and cortex-a15 have pmus	Andrew Jones	1	-0/+3
2019-03-25	target/arm: fix crash on pmu register access	Andrew Jones	1	-0/+4
2019-03-25	target/arm: Fix non-parallel expansion of CASP	Richard Henderson	1	-1/+1
2019-03-23	target/xtensa: don't announce exit simcall	Max Filippov	1	-1/+0
2019-03-22	trace-events: Shorten file names in comments	Markus Armbruster	7	-17/+17
2019-03-22	target/riscv: Zero extend the inputs of divuw and remuw	Palmer Dabbelt	2	-2/+23
2019-03-21	target/xtensa: fix break_dependency for repeated resources	Max Filippov	1	-1/+0
2019-03-20	i386: Disable OSPKE on CPU model definitions	Eduardo Habkost	1	-3/+3
2019-03-20	i386: Make arch_capabilities migratable	Eduardo Habkost	1	-1/+0
2019-03-20	i386: kvm: Disable arch_capabilities if MSR can't be set	Eduardo Habkost	1	-0/+9
2019-03-19	target/riscv: Remove unused struct	Alistair Francis	1	-6/+0
2019-03-19	RISC-V: Update load reservation comment in do_interrupt	Michael Clark	1	-1/+7
2019-03-19	RISC-V: Convert trap debugging to trace events	Michael Clark	2	-9/+5
2019-03-19	RISC-V: Add support for vectored interrupts	Michael Clark	2	-97/+60
2019-03-19	RISC-V: Change local interrupts from edge to level	Michael Clark	1	-2/+2
2019-03-19	RISC-V: linux-user support for RVE ABI	Kito Cheng	2	-1/+6
2019-03-19	RISC-V: Allow interrupt controllers to claim interrupts	Michael Clark	3	-8/+15
2019-03-19	riscv: pmp: Log pmp access errors as guest errors	Alistair Francis	1	-7/+13
2019-03-19	RISC-V: Add hooks to use the gdb xml files.	Jim Wilson	3	-12/+349
2019-03-19	RISC-V: Add debug support for accessing CSRs.	Jim Wilson	2	-7/+30
2019-03-19	RISC-V: Fixes to CSR_* register macros.	Jim Wilson	1	-2/+33
2019-03-18	target/i386: sev: Do not pin the ram device memory region	Singh, Brijesh	1	-0/+11
2019-03-17	target/riscv: Fix manually parsed 16 bit insn	Bastian Koppelmann	1	-5/+25
2019-03-15	target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXIT	Richard Henderson	1	-14/+28
2019-03-15	target/arm: Check access permission to ADDVL/ADDPL/RDVL	Amir Charif	1	-8/+14
2019-03-15	target/arm: change arch timer registers access permission	Dongjiu Geng	1	-15/+15
2019-03-13	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf4' i...	Peter Maydell	12	-1589/+2891
2019-03-13	target/riscv: Remove decode_RV32_64G()	Bastian Koppelmann	1	-20/+1
2019-03-13	target/riscv: Remove gen_system()	Bastian Koppelmann	1	-34/+0
2019-03-13	target/riscv: Rename trans_arith to gen_arith	Bastian Koppelmann	3	-18/+18
2019-03-13	target/riscv: Remove manual decoding of RV32/64M insn	Bastian Koppelmann	2	-211/+164
2019-03-13	target/riscv: Remove shift and slt insn manual decoding	Bastian Koppelmann	2	-71/+81
2019-03-13	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	Bastian Koppelmann	3	-30/+34
2019-03-13	target/riscv: Move gen_arith_imm() decoding into trans_* functions	Bastian Koppelmann	3	-100/+108
2019-03-13	target/riscv: Remove manual decoding from gen_store()	Bastian Koppelmann	2	-11/+24
2019-03-13	target/riscv: Remove manual decoding from gen_load()	Bastian Koppelmann	2	-16/+25