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2020-03-26linux-user/i386: Emulate x86_64 vsyscallsRichard Henderson2-1/+20
2020-03-26target/i386: Renumber EXCP_SYSCALLRichard Henderson1-3/+2
2020-03-24hw/ppc: Take QEMU lock when calling ppc_dcr_read/write()Peter Maydell1-14/+26
2020-03-24target/ppc: Fix ISA v3.0 (POWER9) slbia implementationNicholas Piggin3-9/+54
2020-03-24target/ppc: Fix slbia TLB invalidation gapNicholas Piggin1-6/+15
2020-03-23target/arm: Move computation of index in handle_simd_dupeRichard Henderson1-1/+2
2020-03-23target/arm: Assert immh != 0 in disas_simd_shift_immRichard Henderson1-0/+3
2020-03-23target/arm: Rearrange disabled check for watchpointsRichard Henderson1-5/+6
2020-03-19target/rx: Dump bytes for each insn during disassemblyRichard Henderson1-1/+15
2020-03-19target/rx: Collect all bytes during disassemblyRichard Henderson1-20/+42
2020-03-19target/rx: Emit all disassembly in one prt()Richard Henderson1-36/+39
2020-03-19target/rx: Use prt_ldmi for XCHG_mr disassemblyRichard Henderson1-7/+1
2020-03-19target/rx: Replace operand with prt_ldmi in disassemblerRichard Henderson1-50/+27
2020-03-19target/rx: Disassemble rx_index_addr into a stringRichard Henderson1-99/+55
2020-03-19target/rx: RX disassemblerYoshinori Sato1-0/+1480
2020-03-19target/rx: CPU definitionsYoshinori Sato7-6/+612
2020-03-19target/rx: TCG helpersYoshinori Sato3-0/+650
2020-03-19target/rx: TCG translationYoshinori Sato3-0/+3065
2020-03-19Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell39-106/+243
2020-03-18Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-gdbstub-1...Peter Maydell38-202/+471
2020-03-18Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2020-03-17' into...Peter Maydell1-6/+2
2020-03-18Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200317' into...Peter Maydell8-324/+251
2020-03-17hw/i386: Update structures to save the number of nodes per packageBabu Moger2-0/+2
2020-03-17hw/i386: Consolidate topology functionsBabu Moger1-12/+11
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell38-87/+93
2020-03-17i386: Add 2nd Generation AMD EPYC processorsMoger, Babu2-1/+103
2020-03-17i386: Add missing cpu feature bits in EPYC modelMoger, Babu1-4/+13
2020-03-17target/i386: Add new property note to versioned CPU modelsTao Xu1-2/+9
2020-03-17target/i386: Add Denverton-v2 (no MPX) CPU modelTao Xu1-0/+12
2020-03-17Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell7-222/+145
2020-03-17target/arm: don't bother with id_aa64pfr0_read for USER_ONLYAlex Bennée1-5/+15
2020-03-17target/arm: generate xml description of our SVE registersAlex Bennée3-5/+261
2020-03-17target/arm: default SVE length to 64 bytes for linux-userAlex Bennée1-3/+4
2020-03-17target/arm: explicitly encode regnum in our XMLAlex Bennée3-8/+13
2020-03-17target/arm: prepare for multiple dynamic XMLsAlex Bennée3-24/+30
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée37-119/+126
2020-03-17target/i386: use gdb_get_reg helpersAlex Bennée1-16/+11
2020-03-17target/m68k: use gdb_get_reg helpersAlex Bennée1-18/+11
2020-03-17target/arm: use gdb_get_reg helpersAlex Bennée1-11/+7
2020-03-17Use &error_abort instead of separate assert()Markus Armbruster1-6/+2
2020-03-17target/ppc: allow ppc_cpu_do_system_reset to take an alternate vectorNicholas Piggin2-2/+5
2020-03-17ppc/spapr: Fix FWNMI machine check interrupt deliveryNicholas Piggin2-22/+53
2020-03-17target/ppc: Fix rlwinm on ppc64Vitaly Chikunov1-9/+11
2020-03-16target/riscv: Fix VS mode interrupts forwarding.Rajnesh Kanwal1-1/+8
2020-03-16target/riscv: Correctly implement TSR trapAlistair Francis1-1/+1
2020-03-17spapr,ppc: Simplify signature of kvmppc_rma_size()David Gibson2-7/+5
2020-03-17target/ppc: Don't store VRMA SLBE persistentlyDavid Gibson2-60/+35
2020-03-17target/ppc: Only calculate RMLS derived RMA limit on demandDavid Gibson2-4/+6
2020-03-17target/ppc: Correct RMLS tableDavid Gibson1-3/+4
2020-03-17target/ppc: Streamline calculation of RMA limit from LPCR[RMLS]David Gibson1-36/+27