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2021-06-28Merge remote-tracking branch 'remotes/philmd/tags/mips-20210625' into stagingPeter Maydell15-70/+41
MIPS patches queue Various fixes: - Potential integer overflow (CID 1452921) - Invalid emulation of nanoMIPS BPOSGE32 opcode - Missing exception when DINSV opcode used with DSP disabled - Do not abort but emit exception for invalid BRANCH opcodes - TCG temporary leaks Housekeeping: - Remove dead code / comments - Restrict few files to TCG, declarations to sysemu - Merge MSA32 and MSA64 decodetree definitions # gpg: Signature made Fri 25 Jun 2021 10:22:20 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/mips-20210625: target/mips: Merge msa32/msa64 decodetree definitions target/mips: Remove pointless gen_msa() target/mips: Optimize regnames[] arrays target/mips: Constify host_to_mips_errno[] target/mips: fix emulation of nanoMIPS BPOSGE32 instruction target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases target/mips: Remove SmartMIPS / MDMX unuseful comments target/mips: Restrict some system specific declarations to sysemu target/mips: Move translate.h to tcg/ sub directory target/mips: Move TCG trace events to tcg/ sub directory target/mips: Do not abort on invalid instruction target/mips: Raise exception when DINSV opcode used with DSP disabled target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insn target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn() target/mips: Fix potential integer overflow (CID 1452921) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-25Merge remote-tracking branch ↵Peter Maydell2-2/+2
'remotes/alistair/tags/pull-riscv-to-apply-20210624-2' into staging Third RISC-V PR for 6.1 release - Fix MISA in the DisasContext - Fix GDB CSR XML generation - QOMify the SiFive UART - Add support for the OpenTitan timer # gpg: Signature made Thu 24 Jun 2021 13:00:26 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210624-2: hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer hw/timer: Initial commit of Ibex Timer hw/char/ibex_uart: Make the register layout private hw/char: QOMify sifive_uart hw/char: Consistent function names for sifive_uart target/riscv: gdbstub: Fix dynamic CSR XML generation target/riscv: Use target_ulong for the DisasContext misa Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-24target/mips: Merge msa32/msa64 decodetree definitionsPhilippe Mathieu-Daudé4-32/+10
We don't need to maintain 2 sets of decodetree definitions. Merge them into a single file. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174636.2902654-3-f4bug@amsat.org>
2021-06-24target/mips: Remove pointless gen_msa()Philippe Mathieu-Daudé1-6/+1
Only trans_MSA() calls gen_msa(), inline it to simplify. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174636.2902654-2-f4bug@amsat.org>
2021-06-24target/mips: Optimize regnames[] arraysPhilippe Mathieu-Daudé5-7/+7
Since all entries are no more than 3/4/6 bytes (including nul terminator), can save space and pie runtime relocations by declaring regnames[] as array of 3/4/6 const char. Inspired-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-10-f4bug@amsat.org>
2021-06-24target/mips: Constify host_to_mips_errno[]Philippe Mathieu-Daudé1-1/+1
Keep host_to_mips_errno[] in .rodata by marking the array const. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-9-f4bug@amsat.org>
2021-06-24target/mips: fix emulation of nanoMIPS BPOSGE32 instructionAleksandar Rikalo1-1/+1
Per the "MIPS® Architecture Extension: nanoMIPS32 DSP Technical Reference Manual — Revision 0.04" p. 88 "BPOSGE32C", offset argument (imm) should be left-shifted first. This change was tested against test_dsp_r1_bposge32.c DSP test. Reported-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Filip Vidojevic <filip.vidojevic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <VI1PR0302MB34869449EE56F226FC3C21129C309@VI1PR0302MB3486.eurprd03.prod.outlook.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-06-24target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful casesPhilippe Mathieu-Daudé1-6/+0
These switch cases for the microMIPS BPOSGE32 / BPOSGE64 opcodes have been added commit 3c824109da0 ("target-mips: microMIPS ASE support"). More than 11 years later it is safe to assume there won't be added soon. The cases fall back to the default which generates a RESERVED INSTRUCTION, so it is safe to remove them. Functionally speaking, the patch is a no-op. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-8-f4bug@amsat.org>
2021-06-24target/mips: Remove SmartMIPS / MDMX unuseful commentsPhilippe Mathieu-Daudé1-8/+0
These placeholder comments for SmartMIPS and MDMX extensions have been added commit 3c824109da0 ("target-mips: microMIPS ASE support"). More than 11 years later it is safe to assume there won't be added soon, so remove these unuseful comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-7-f4bug@amsat.org>
2021-06-24target/mips: Restrict some system specific declarations to sysemuPhilippe Mathieu-Daudé1-3/+7
Commit 043715d1e0f ("target/mips: Update ITU to utilize SAARI and SAAR CP0 registers") declared itc_reconfigure() in public namespace, while it is restricted to system emulation. Similarly commit 5679479b9a1 ("target/mips: Move CP0 helpers to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to system emulation, but forgot to restrict its declaration. To avoid polluting user-mode emulation with these declarations, restrict them to sysemu. Also restrict the sysemu ITU/ITC/IRQ fields from CPUMIPSState. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-6-f4bug@amsat.org>
2021-06-24target/mips: Move translate.h to tcg/ sub directoryPhilippe Mathieu-Daudé1-0/+0
We moved various TCG source files in commit a2b0a27d33e ("target/mips: Move TCG source files under tcg/ sub directory") but forgot to move the header declaring their prototypes. Do it now, since all it declares is TCG specific. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-5-f4bug@amsat.org>
2021-06-24target/mips: Move TCG trace events to tcg/ sub directoryPhilippe Mathieu-Daudé4-2/+2
Commit a2b0a27d33e ("target/mips: Move TCG source files under tcg/ sub directory") forgot to move the trace-event file. As it only contains TCG events, move it for consistency. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-4-f4bug@amsat.org>
2021-06-24target/mips: Do not abort on invalid instructionPhilippe Mathieu-Daudé1-2/+2
On real hardware an invalid instruction doesn't halt the world, but usually triggers a RESERVED INSTRUCTION exception. TCG guest code shouldn't abort QEMU anyway. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-2-f4bug@amsat.org>
2021-06-24target/mips: Raise exception when DINSV opcode used with DSP disabledPhilippe Mathieu-Daudé1-1/+2
Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02, Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module": If the Module/ASE is not implemented, executing such an instruction must cause a Reserved Instruction Exception. The DINSV instruction lists the following exceptions: - Reserved Instruction - DSP Disabled If the MIPS core doesn't support the DSP module, or the DSP is disabled, do not handle the '$rt = $0' case as a no-op but raise the proper exception instead. Cc: Jia Liu <proljc@gmail.com> Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210529165443.1114402-1-f4bug@amsat.org>
2021-06-24target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insnPhilippe Mathieu-Daudé1-0/+4
Fix multiple TCG temporary leaks in gen_pool32a5_nanomips_insn(). Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS - part 1") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-3-f4bug@amsat.org>
2021-06-24target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn()Philippe Mathieu-Daudé1-0/+2
Fix a pair of TCG temporary leak when translating nanoMIPS SHILO opcode. Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210530094538.1275329-1-f4bug@amsat.org>
2021-06-24target/mips: Fix potential integer overflow (CID 1452921)Philippe Mathieu-Daudé1-1/+2
Use the BIT_ULL() macro to ensure we use 64-bit arithmetic. This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN): CID 1452921: Integer handling issues: Potentially overflowing expression "1 << w" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). Fixes: 074cfcb4dae ("target/mips: Implement hardware page table walker") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210505215119.1517465-1-f4bug@amsat.org>
2021-06-24Merge remote-tracking branch ↵Peter Maydell16-615/+3347
'remotes/pmaydell/tags/pull-target-arm-20210624' into staging target-arm queue: * Don't require 'virt' board to be compiled in for ACPI GHES code * docs: Document which architecture extensions we emulate * Fix bugs in M-profile FPCXT_NS accesses * First slice of MVE patches * Implement MTE3 * docs/system: arm: Add nRF boards description # gpg: Signature made Thu 24 Jun 2021 14:59:16 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210624: (57 commits) docs/system: arm: Add nRF boards description target/arm: Implement MTE3 target/arm: Make VMOV scalar <-> gpreg beatwise for MVE target/arm: Implement MVE VADDV target/arm: Implement MVE VHCADD target/arm: Implement MVE VCADD target/arm: Implement MVE VADC, VSBC target/arm: Implement MVE VRHADD target/arm: Implement MVE VQDMULL (vector) target/arm: Implement MVE VQDMLSDH and VQRDMLSDH target/arm: Implement MVE VQDMLADH and VQRDMLADH target/arm: Implement MVE VRSHL target/arm: Implement MVE VSHL insn target/arm: Implement MVE VQRSHL target/arm: Implement MVE VQSHL (vector) target/arm: Implement MVE VQADD, VQSUB (vector) target/arm: Implement MVE VQDMULH, VQRDMULH (vector) target/arm: Implement MVE VQDMULL scalar target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) target/arm: Implement MVE VQADD and VQSUB ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-24target/arm: Implement MTE3Peter Collingbourne2-32/+52
MTE3 introduces an asymmetric tag checking mode, in which loads are checked synchronously and stores are checked asynchronously. Add support for it. Signed-off-by: Peter Collingbourne <pcc@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210616195614.11785-1-pcc@google.com [PMM: Add line to emulation.rst] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-24target/arm: Make VMOV scalar <-> gpreg beatwise for MVEPeter Maydell3-8/+75
In a CPU with MVE, the VMOV (vector lane to general-purpose register) and VMOV (general-purpose register to vector lane) insns are not predicated, but they are subject to beatwise execution if they are not in an IT block. Since our implementation always executes all 4 beats in one tick, this means only that we need to handle PSR.ECI: * we must do the usual check for bad ECI state * we must advance ECI state if the insn succeeds * if ECI says we should not be executing the beat corresponding to the lane of the vector register being accessed then we should skip performing the move Note that if PSR.ECI is non-zero then we cannot be in an IT block. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-45-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VADDVPeter Maydell4-0/+76
Implement the MVE VADDV insn, which performs an addition across vector lanes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-44-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VHCADDPeter Maydell4-3/+19
Implement the MVE VHCADD insn, which is similar to VCADD but performs a halving step. This one overlaps with VADC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-43-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VCADDPeter Maydell4-2/+51
Implement the MVE VCADD insn, which performs a complex add with rotate. Note that the size=0b11 encoding is VSBC. The architecture grants some leeway for the "destination and Vm source overlap" case for the size MO_32 case, but we choose not to make use of it, instead always calculating all 16 bytes worth of results before setting the destination register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-42-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VADC, VSBCPeter Maydell4-0/+99
Implement the MVE VADC and VSBC insns. These perform an add-with-carry or subtract-with-carry of the 32-bit elements in each lane of the input vectors, where the carry-out of each add is the carry-in of the next. The initial carry input is either 1 or is from FPSCR.C; the carry out at the end is written back to FPSCR.C. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-41-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VRHADDPeter Maydell4-0/+19
Implement the MVE VRHADD insn, which performs a rounded halving addition. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-40-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQDMULL (vector)Peter Maydell4-0/+70
Implement the vector form of the MVE VQDMULL insn. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-39-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQDMLSDH and VQRDMLSDHPeter Maydell4-0/+69
Implement the MVE VQDMLSDH and VQRDMLSDH insns, which are like VQDMLADH and VQRDMLADH except that products are subtracted rather than added. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-38-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQDMLADH and VQRDMLADHPeter Maydell4-0/+114
Implement the MVE VQDMLADH and VQRDMLADH insns. These multiply elements, and then add pairs of products, double, possibly round, saturate and return the high half of the result. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-37-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VRSHLPeter Maydell4-0/+17
Implement the MVE VRSHL insn (vector form). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-36-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VSHL insnPeter Maydell4-0/+19
Implement the MVE VSHL insn (vector form). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-35-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQRSHLPeter Maydell4-0/+19
Implement the MV VQRSHL (vector) insn. Again, the code to perform the actual shifts is borrowed from neon_helper.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-34-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQSHL (vector)Peter Maydell4-0/+56
Implement the MVE VQSHL insn (encoding T4, which is the vector-shift-by-vector version). The DO_SQSHL_OP and DO_UQSHL_OP macros here are derived from the neon_helper.c code for qshl_u{8,16,32} and qshl_s{8,16,32}. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-33-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQADD, VQSUB (vector)Peter Maydell4-0/+39
Implement the vector forms of the MVE VQADD and VQSUB insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-32-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQDMULH, VQRDMULH (vector)Peter Maydell4-0/+40
Implement the vector forms of the MVE VQDMULH and VQRDMULH insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-31-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQDMULL scalarPeter Maydell4-4/+119
Implement the MVE VQDMULL scalar insn. This multiplies the top or bottom half of each element by the scalar, doubles and saturates to a double-width result. Note that this encoding overlaps with VQADD and VQSUB; it uses what in VQADD and VQSUB would be the 'size=0b11' encoding. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-30-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)Peter Maydell4-0/+38
Implement the MVE VQDMULH and VQRDMULH scalar insns, which multiply elements by the scalar, double, possibly round, take the high half and saturate. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-29-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VQADD and VQSUBPeter Maydell4-0/+87
Implement the MVE VQADD and VQSUB insns, which perform saturating addition of a scalar to each element. Note that individual bytes of each result element are used or discarded according to the predicate mask, but FPSCR.QC is only set if the predicate mask for the lowest byte of the element is set. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-28-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VPSTPeter Maydell2-0/+63
Implement the MVE VPST insn, which sets the predicate mask fields in the VPR to the immediate value encoded in the insn. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-27-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VBRSRPeter Maydell4-0/+49
Implement the MVE VBRSR insn, which reverses a specified number of bits in each element, setting the rest to zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-26-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VHADD, VHSUB (scalar)Peter Maydell4-0/+32
Implement the scalar variants of the MVE VHADD and VHSUB insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-25-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VSUB, VMUL (scalar)Peter Maydell4-0/+14
Implement the scalar forms of the MVE VSUB and VMUL insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-24-peter.maydell@linaro.org
2021-06-24target/arm: Implement MVE VADD (scalar)Peter Maydell4-0/+78
Implement the scalar form of the MVE VADD insn. This takes the scalar operand from a general purpose register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-23-peter.maydell@linaro.org
2021-06-24target/riscv: gdbstub: Fix dynamic CSR XML generationBin Meng1-1/+1
Since commit 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations") the CSR predicate() function was changed to return RISCV_EXCP_NONE instead of 0 for a valid CSR, but it forgot to update the dynamic CSR XML generation codes in gdbstub. Fixes: 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations") Reported-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Tested-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210615085133.389887-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-24target/riscv: Use target_ulong for the DisasContext misaAlistair Francis1-1/+1
The is_32bit() check in translate.c expects a 64-bit guest to have a 64-bit misa value otherwise the macro check won't work. This patches fixes that and fixes a Coverity issue at the same time. Fixes: CID 1453107 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: c00176c7518c2a7b4de3eec320b6a683ab56f705.1622435221.git.alistair.francis@wdc.com
2021-06-22Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210621' ↵Peter Maydell18-565/+1496
into staging s390x update: - tcg: implement the vector enhancements facility and bump the 'qemu' cpu model to a stripped-down z14 GA2 - fix psw.mask handling in signals - fix vfio-ccw sense data handling # gpg: Signature made Mon 21 Jun 2021 10:53:00 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck-gitlab/tags/s390x-20210621: (37 commits) s390x/css: Add passthrough IRB s390x/css: Refactor IRB construction s390x/css: Split out the IRB sense data s390x/css: Introduce an ESW struct linux-user/s390x: Save and restore psw.mask properly target/s390x: Use s390_cpu_{set_psw, get_psw_mask} in gdbstub target/s390x: Improve s390_cpu_dump_state vs cc_op target/s390x: Do not modify cpu state in s390_cpu_get_psw_mask target/s390x: Expose load_psw and get_psw_mask to cpu.h configure: Check whether we can compile the s390-ccw bios with -msoft-float s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2 s390x/tcg: We support Vector enhancements facility linux-user: elf: s390x: Prepare for Vector enhancements facility s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM) s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT) s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT) s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-22Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210619-2' ↵Peter Maydell4-10/+0
into staging TCI cleanup and re-encoding Fixes for #367 and #390. Move TCGCond to tcg/tcg-cond.h. Fix for win32 qemu_try_memalign. # gpg: Signature made Sun 20 Jun 2021 05:23:53 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210619-2: (33 commits) util/oslib-win32: Fix fatal assertion in qemu_try_memalign tcg: expose TCGCond manipulation routines tcg: Restart when exhausting the stack frame tcg: Allocate sufficient storage in temp_allocate_frame tcg/sparc: Fix temp_allocate_frame vs sparc stack bias accel/tcg: Probe the proper permissions for atomic ops tests/tcg: Increase timeout for TCI tcg/tci: Use {set,clear}_helper_retaddr tcg/tci: Remove the qemu_ld/st_type macros Revert "tcg/tci: Use exec/cpu_ldst.h interfaces" tcg/tci: Split out tci_qemu_ld, tci_qemu_st tcg/tci: Implement add2, sub2 tcg/tci: Implement mulu2, muls2 tcg/tci: Implement clz, ctz, ctpop tcg/tci: Implement extract, sextract tcg/tci: Implement andc, orc, eqv, nand, nor tcg/tci: Implement movcond tcg/tci: Implement goto_ptr tcg/tci: Change encoding to uint32_t units tcg/tci: Remove tci_write_reg ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-21target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVHPeter Maydell4-0/+76
Implement the MVE VRMLALDAVH and VRMLSLDAVH insns, which accumulate the results of a rounded multiply of pairs of elements into a 72-bit accumulator, returning the top 64 bits in a pair of general purpose registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-22-peter.maydell@linaro.org
2021-06-21target/arm: Implement MVE VMLSLDAVPeter Maydell4-0/+23
Implement the MVE insn VMLSLDAV, which multiplies source elements, alternately adding and subtracting them, and accumulates into a 64-bit result in a pair of general purpose registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-21-peter.maydell@linaro.org
2021-06-21target/arm: Implement MVE VMLALDAVPeter Maydell5-0/+163
Implement the MVE VMLALDAV insn, which multiplies pairs of integer elements, accumulating them into a 64-bit result in a pair of general-purpose registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-20-peter.maydell@linaro.org
2021-06-21target/arm: Implement MVE VMULLPeter Maydell4-0/+57
Implement the MVE VMULL insn, which multiplies two single width integer elements to produce a double width result. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-19-peter.maydell@linaro.org
generated by cgit v1.1 at 2025-01-04 12:21:01 +0000