riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-06-21	target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr()	Bastian Koppelmann	1	-1/+6
2023-06-21	target/tricore: ENABLE exit to main-loop	Bastian Koppelmann	1	-0/+5
2023-06-21	target/tricore: Introduce DISAS_TARGET_EXIT	Bastian Koppelmann	1	-13/+12
2023-06-21	target/tricore: Fix RR_JLI clobbering reg A[11]	Bastian Koppelmann	1	-1/+1
2023-06-21	target/tricore: Fix helper_ret() not correctly restoring PSW	Bastian Koppelmann	1	-4/+4
2023-06-21	target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regs	Bastian Koppelmann	1	-2/+9
2023-06-21	target/tricore: Correctly fix saving PSW.CDE to CSA on call	Bastian Koppelmann	1	-1/+6
2023-06-21	target/tricore: Fix out-of-bounds index in imask instruction	Siqi Chen	1	-0/+1
2023-06-21	target/tricore: Add DISABLE insn variant	Bastian Koppelmann	2	-1/+11
2023-06-21	target/tricore: Implement SYCSCALL insn	Bastian Koppelmann	1	-1/+1
2023-06-21	target/tricore: Add shuffle insn	Bastian Koppelmann	4	-0/+46
2023-06-21	target/tricore: Add crc32.b insn	Bastian Koppelmann	4	-0/+17
2023-06-21	target/tricore: Add crc32l.w insn	Bastian Koppelmann	4	-5/+23
2023-06-21	target/tricore: Add LHA insn	Bastian Koppelmann	2	-3/+20
2023-06-21	target/tricore: Add popcnt.w insn	Bastian Koppelmann	2	-0/+8
2023-06-21	target/tricore: Introduce ISA 1.6.2 feature	Bastian Koppelmann	2	-0/+14
2023-06-20	meson: Replace softmmu_ss -> system_ss	Philippe Mathieu-Daudé	30	-73/+73
2023-06-20	meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLY	Philippe Mathieu-Daudé	1	-1/+1
2023-06-20	target/ppc: Check for USER_ONLY definition instead of SOFTMMU one	Philippe Mathieu-Daudé	2	-14/+12
2023-06-20	target/m68k: Check for USER_ONLY definition instead of SOFTMMU one	Philippe Mathieu-Daudé	4	-25/+23
2023-06-20	target/tricore: Remove pointless CONFIG_SOFTMMU guard	Philippe Mathieu-Daudé	1	-2/+0
2023-06-20	target/i386: Simplify i386_tr_init_disas_context()	Philippe Mathieu-Daudé	1	-3/+0
2023-06-19	target/arm: Convert load/store tags insns to decodetree	Peter Maydell	2	-177/+190
2023-06-19	target/arm: Convert load/store single structure to decodetree	Peter Maydell	2	-108/+127
2023-06-19	target/arm: Convert load/store (multiple structures) to decodetree	Peter Maydell	2	-108/+128
2023-06-19	target/arm: Convert LDAPR/STLR (imm) to decodetree	Peter Maydell	2	-84/+54
2023-06-19	target/arm: Convert load (pointer auth) insns to decodetree	Peter Maydell	2	-67/+23
2023-06-19	target/arm: Convert atomic memory ops to decodetree	Peter Maydell	2	-98/+70
2023-06-19	target/arm: Convert LDR/STR reg+reg to decodetree	Peter Maydell	2	-87/+98
2023-06-19	target/arm: Convert LDR/STR with 12-bit immediate to decodetree	Peter Maydell	2	-88/+41
2023-06-19	target/arm: Convert ld/st reg+imm9 insns to decodetree	Peter Maydell	2	-118/+149
2023-06-19	target/arm: Convert load/store-pair to decodetree	Peter Maydell	2	-196/+249
2023-06-19	target/arm: Convert load reg (literal) group to decodetree	Peter Maydell	2	-54/+35
2023-06-19	target/arm: Convert LDXP, STXP, CASP, CAS to decodetree	Peter Maydell	2	-76/+50
2023-06-19	target/arm: Convert load/store exclusive and ordered to decodetree	Peter Maydell	2	-62/+103
2023-06-19	target/arm: Convert exception generation instructions to decodetree	Peter Maydell	2	-106/+76
2023-06-19	target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree	Peter Maydell	2	-28/+14
2023-06-19	target/arm: Convert MSR (immediate) to decodetree	Peter Maydell	2	-115/+123
2023-06-19	target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree	Peter Maydell	2	-27/+32
2023-06-19	target/arm: Convert barrier insns to decodetree	Peter Maydell	2	-53/+46
2023-06-19	target/arm: Convert hint instruction space to decodetree	Peter Maydell	2	-123/+185
2023-06-19	target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores	Peter Maydell	1	-4/+6
2023-06-19	target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode	Peter Maydell	1	-1/+1
2023-06-19	target/arm: Return correct result for LDG when ATA=0	Peter Maydell	1	-1/+5
2023-06-19	target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics	Peter Maydell	1	-2/+16
2023-06-16	Merge tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu into s...	Richard Henderson	2	-2/+4
2023-06-16	target/loongarch: Fix CSR.DMW0-3.VSEG check	Jiajie Chen	1	-2/+2
2023-06-16	hw/intc: Set physical cpuid route for LoongArch ipi device	Tianrui Zhao	1	-0/+2
2023-06-15	target/arm: Allow users to set the number of VFP registers	Cédric Le Goater	2	-0/+34
2023-06-14	Merge tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qem...	Richard Henderson	17	-498/+698