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2019-12-17x86: move more x86-generic functions out of PC filesPaolo Bonzini2-2/+2
2019-12-17x86: move SMM property to X86MachineStatePaolo Bonzini1-2/+1
2019-12-17hw: replace hw/i386/pc.h with a header just for the i8259Paolo Bonzini1-1/+0
2019-12-17kvm: introduce kvm_kernel_irqchip_* functionsPaolo Bonzini5-9/+9
2019-12-17kvm: convert "-machine kvm_shadow_mem" to an accelerator propertyPaolo Bonzini1-1/+1
2019-12-17qom: add object_new_with_classPaolo Bonzini2-6/+6
2019-12-17Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20191217' into...Peter Maydell10-28/+335
2019-12-17Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' in...Peter Maydell2-28/+76
2019-12-17target/ppc: Add SPR TBU40Suraj Jitindar Singh4-0/+26
2019-12-17target/ppc: Add SPR ASDRSuraj Jitindar Singh2-0/+7
2019-12-17target/ppc: Work [S]PURR implementation and add HV supportSuraj Jitindar Singh4-8/+22
2019-12-17target/ppc: Implement the VTB for HV accessSuraj Jitindar Singh4-4/+29
2019-12-17target/ppc: Add POWER10 DD1.0 model informationCédric Le Goater5-6/+237
2019-12-17ppc: Make PPCVirtualHypervisor an incomplete typeGreg Kurz1-4/+0
2019-12-17ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVMGreg Kurz1-0/+5
2019-12-17ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU modelsGreg Kurz1-1/+3
2019-12-17ppc: Deassert the external interrupt pin in KVM on resetGreg Kurz1-0/+1
2019-12-17ppc: well form kvmppc_hint_smt_possible error hint helperVladimir Sementsov-Ogievskiy2-5/+5
2019-12-16Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191216-...Peter Maydell11-16/+294
2019-12-16target/arm: ensure we use current exception state after SCR updateAlex Bennée4-4/+25
2019-12-16target/arm: Add support for DC CVAP & DC CVADP insBeata Michalska3-0/+67
2019-12-16arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on()Niek Linnenbank1-0/+3
2019-12-16target/arm: Add support for missing Jazelle system registersMarc Zyngier1-0/+27
2019-12-16target/arm: Handle AArch32 CP15 trapping via HSTR_EL2Marc Zyngier5-1/+34
2019-12-16target/arm: Handle trapping to EL2 of AArch32 VMRS instructionsMarc Zyngier3-3/+46
2019-12-16target/arm: Honor HCR_EL2.TID1 trapping requirementsMarc Zyngier1-4/+32
2019-12-16target/arm: Honor HCR_EL2.TID2 trapping requirementsMarc Zyngier1-4/+27
2019-12-16target/arm: Add support for cortex-m7 CPUChristophe Lyon1-0/+33
2019-12-14s390x/tcg: clear local interrupts on reset normalCornelia Huck1-4/+4
2019-12-14s390x/cpumodel: Fix query-cpu-definitions error API violationsMarkus Armbruster1-5/+1
2019-12-14s390x/cpumodel: Fix query-cpu-model-FOO error API violationsMarkus Armbruster1-16/+27
2019-12-14s390x/cpumodel: Fix realize() error API violationsMarkus Armbruster1-15/+22
2019-12-14s390x/cpumodel: Fix feature property error API violationsMarkus Armbruster1-4/+8
2019-12-14s390x: Fix cpu normal reset ri clearingJanosch Frank2-2/+12
2019-12-14s390x: kvm: Make kvm_sclp_service_call voidJanosch Frank1-7/+5
2019-12-14s390x: Beautify diag308 handlingJanosch Frank1-22/+32
2019-12-14s390x: Move clear resetJanosch Frank2-41/+18
2019-12-14s390x: Move initial resetJanosch Frank4-31/+21
2019-12-14s390x: Move reset normal to shared reset handlerJanosch Frank4-9/+20
2019-12-13i386: Use g_autofree in a few placesEduardo Habkost1-28/+13
2019-12-13i386: Add new CPU model CooperlakeCathy Zhang1-0/+60
2019-12-13i386: Add macro for stibpCathy Zhang1-0/+2
2019-12-13i386: Add MSR feature bit for MDS-NOCathy Zhang1-0/+1
2019-12-06target/i386: disable VMX features if nested=0Yang Zhong1-0/+8
2019-12-03hvf: correctly inject VMCS_INTR_T_HWINTR versus VMCS_INTR_T_SWINTR.Cameron Esfahani2-6/+12
2019-11-26Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell7-72/+104
2019-11-26target/arm: Honor HCR_EL2.TID3 trapping requirementsMarc Zyngier1-0/+76
2019-11-26target/arm: Fix ISR_EL1 tracking when executing at EL2Marc Zyngier1-2/+5
2019-11-26target/arm: Fix handling of cortex-m FTYPE flag in EXCRETJean-Hugues Deschênes1-4/+3
2019-11-26hvf: more accurately match SDM when setting CR0 and PDPTE registersCameron Esfahani2-8/+18
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