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2023-10-19hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h'Philippe Mathieu-Daudé2-3/+1
2023-10-19hw/mips: Merge 'hw/mips/cpudevs.h' with 'target/mips/cpu.h'Philippe Mathieu-Daudé3-3/+3
2023-10-19memory: follow Error API guidelinesMarc-André Lureau2-3/+5
2023-10-17target/hexagon: avoid invalid escape in Python stringPaolo Bonzini1-2/+2
2023-10-17target/i386: check intercept for XSETBVPaolo Bonzini2-0/+2
2023-10-17target/i386/cpu: Fix CPUID_HT exposureXiaoyao Li2-0/+3
2023-10-16Merge tag 'pull-loongarch-20231013' of https://gitlab.com/gaosong/qemu into s...Stefan Hajnoczi4-2/+17
2023-10-16Merge tag 'pull-shadow-2023-10-12' of https://repo.or.cz/qemu/armbru into sta...Stefan Hajnoczi1-1/+1
2023-10-13target/loongarch: Add preldx instructionSong Gao3-0/+15
2023-10-13target/loongarch: fix ASXE flag conflictJiajie Chen1-2/+2
2023-10-12target/i386: fix shadowed variable pastoPaolo Bonzini1-1/+1
2023-10-12target/riscv: Fix vfwmaccbf16.vfMax Chou1-1/+1
2023-10-12target/riscv: deprecate capital 'Z' CPU propertiesDaniel Henrique Barboza3-12/+59
2023-10-12target/riscv: Use env_archcpu for better performanceRichard W.M. Jones1-2/+1
2023-10-12target/riscv/tcg: remove RVG warningDaniel Henrique Barboza1-1/+0
2023-10-12target/riscv/kvm: support KVM_GET_REG_LISTDaniel Henrique Barboza1-1/+95
2023-10-12target/riscv/kvm: improve 'init_multiext_cfg' error msgDaniel Henrique Barboza1-2/+2
2023-10-12target/riscv/tcg-cpu.c: add extension properties for all cpusDaniel Henrique Barboza1-14/+50
2023-10-12target/riscv: add riscv_cpu_get_name()Daniel Henrique Barboza3-1/+15
2023-10-12target/riscv/cpu: move priv spec functions to tcg-cpu.cDaniel Henrique Barboza3-40/+38
2023-10-12target/riscv/cpu.c: export isa_edata_arr[]Daniel Henrique Barboza2-26/+28
2023-10-12target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.cDaniel Henrique Barboza3-91/+90
2023-10-12target/riscv/cpu.c: make misa_ext_cfgs[] 'const'Daniel Henrique Barboza1-13/+8
2023-10-12target/riscv/tcg: introduce tcg_cpu_instance_init()Daniel Henrique Barboza3-151/+149
2023-10-12target/riscv/cpu.c: export set_misa()Daniel Henrique Barboza2-16/+19
2023-10-12target/riscv/kvm: do not use riscv_cpu_add_misa_properties()Daniel Henrique Barboza3-9/+18
2023-10-12target/riscv: move KVM only files to kvm subdirDaniel Henrique Barboza5-2/+3
2023-10-12target/riscv: introduce KVM AccelCPUClassDaniel Henrique Barboza3-8/+27
2023-10-12target/riscv: remove kvm-stub.cDaniel Henrique Barboza2-31/+1
2023-10-12target/riscv: make riscv_add_satp_mode_properties() publicDaniel Henrique Barboza3-3/+4
2023-10-12target/riscv: move riscv_cpu_add_kvm_properties() to kvm.cDaniel Henrique Barboza4-84/+86
2023-10-12target/riscv/cpu.c: mark extensions arrays as 'const'Daniel Henrique Barboza1-9/+13
2023-10-12target/riscv: move 'host' CPU declaration to kvm.cDaniel Henrique Barboza2-15/+21
2023-10-12target/riscv/cpu.c: add .instance_post_init()Daniel Henrique Barboza1-11/+32
2023-10-12target/riscv: move riscv_tcg_ops to tcg-cpu.cDaniel Henrique Barboza3-63/+59
2023-10-12target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.cDaniel Henrique Barboza5-357/+397
2023-10-12target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()Daniel Henrique Barboza2-128/+133
2023-10-12target/riscv: introduce TCG AccelCPUClassDaniel Henrique Barboza5-4/+67
2023-10-12target/riscv: Clear CSR values at reset and sync MPSTATE with hostliguang.zhang2-0/+45
2023-10-12target/riscv/cpu.c: consider user option with RVGDaniel Henrique Barboza1-2/+16
2023-10-12target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()Daniel Henrique Barboza1-0/+16
2023-10-12target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()Daniel Henrique Barboza1-9/+9
2023-10-12target/riscv/cpu.c: introduce RISCVCPUMultiExtConfigDaniel Henrique Barboza1-99/+159
2023-10-12target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()Daniel Henrique Barboza1-25/+25
2023-10-12target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()Daniel Henrique Barboza1-3/+40
2023-10-12target/riscv: make CPUCFG() macro publicDaniel Henrique Barboza3-6/+6
2023-10-12target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabledDaniel Henrique Barboza1-9/+9
2023-10-12target/riscv: deprecate the 'any' CPU typeDaniel Henrique Barboza1-0/+5
2023-10-12target/riscv: add 'max' CPU typeDaniel Henrique Barboza2-0/+57
2023-10-12target/riscv/cpu.c: limit cfg->vext_spec log messageDaniel Henrique Barboza1-5/+4
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