| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-10-24 | target/mips: Add a placeholder for R5900 MMI2 instruction subclass | Fredrik Noring | 1 | -1/+39 |
| 2018-10-24 | target/mips: Add a placeholder for R5900 MMI1 instruction subclass | Fredrik Noring | 1 | -1/+35 |
| 2018-10-24 | target/mips: Add a placeholder for R5900 MMI0 instruction subclass | Fredrik Noring | 1 | -1/+42 |
| 2018-10-24 | target/mips: Add a placeholder for R5900 MMI instruction class | Fredrik Noring | 1 | -1/+44 |
| 2018-10-24 | target/mips: Add a placeholder for R5900 LQ | Fredrik Noring | 1 | -2/+11 |
| 2018-10-24 | target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWR | Fredrik Noring | 1 | -1/+52 |
| 2018-10-24 | target/mips: Define R5900 MMI3 opcode constants | Fredrik Noring | 1 | -0/+39 |
| 2018-10-24 | target/mips: Define R5900 MMI2 opcode constants | Fredrik Noring | 1 | -0/+48 |
| 2018-10-24 | target/mips: Define R5900 MMI1 opcode constants | Fredrik Noring | 1 | -0/+44 |
| 2018-10-24 | target/mips: Define R5900 MMI0 opcode constants | Fredrik Noring | 1 | -0/+51 |
| 2018-10-24 | target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constants | Fredrik Noring | 1 | -0/+51 |
| 2018-10-24 | target/mips: Define R5900 MMI class, and LQ and SQ opcode constants | Fredrik Noring | 1 | -0/+40 |
| 2018-10-24 | target/mips: Add R5900 Multimedia Instruction overview note | Fredrik Noring | 1 | -0/+161 |
| 2018-10-24 | target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants | Fredrik Noring | 1 | -0/+3 |
| 2018-10-24 | target/arm: Only flush tlb if ASID changes | Richard Henderson | 1 | -5/+3 |
| 2018-10-24 | target/arm: Remove writefn from TTBR0_EL3 | Richard Henderson | 1 | -1/+1 |
| 2018-10-24 | target/arm: Reorg NEON VLD/VST single element to one lane | Richard Henderson | 1 | -42/+50 |
| 2018-10-24 | target/arm: Promote consecutive memory ops for aa32 | Richard Henderson | 1 | -0/+10 |
| 2018-10-24 | target/arm: Reorg NEON VLD/VST all elements | Richard Henderson | 1 | -96/+74 |
| 2018-10-24 | target/arm: Use gvec for NEON VLD all lanes | Richard Henderson | 1 | -55/+26 |
| 2018-10-24 | target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE | Richard Henderson | 3 | -61/+60 |
| 2018-10-24 | target/arm: Use gvec for NEON_3R_VML | Richard Henderson | 3 | -122/+120 |
| 2018-10-24 | target/arm: Use gvec for VSRI, VSLI | Richard Henderson | 3 | -219/+179 |
| 2018-10-24 | target/arm: Use gvec for VSRA | Richard Henderson | 3 | -117/+130 |
| 2018-10-24 | target/arm: Use gvec for VSHR, VSHL | Richard Henderson | 1 | -22/+48 |
| 2018-10-24 | target/arm: Use gvec for NEON_3R_VMUL | Richard Henderson | 1 | -16/+15 |
| 2018-10-24 | target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG | Richard Henderson | 1 | -8/+8 |
| 2018-10-24 | target/arm: Use gvec for NEON_3R_VADD_VSUB insns | Richard Henderson | 1 | -19/+10 |
| 2018-10-24 | target/arm: Use gvec for NEON_3R_LOGIC insns | Richard Henderson | 3 | -105/+124 |
| 2018-10-24 | target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate) | Richard Henderson | 1 | -25/+36 |
| 2018-10-24 | target/arm: Use gvec for NEON VDUP | Richard Henderson | 1 | -27/+36 |
| 2018-10-24 | target/arm: Mark some arrays const | Richard Henderson | 1 | -2/+2 |
| 2018-10-24 | target/arm: Promote consecutive memory ops for aa64 | Richard Henderson | 1 | -26/+40 |
| 2018-10-24 | target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R | Richard Henderson | 1 | -25/+3 |
| 2018-10-24 | target/arm: Don't call tcg_clear_temp_count | Richard Henderson | 2 | -2/+0 |
| 2018-10-24 | target/arm: Hoist address increment for vector memory ops | Richard Henderson | 1 | -4/+8 |
| 2018-10-24 | target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode | Peter Maydell | 3 | -5/+26 |
| 2018-10-24 | target/arm: Get IL bit correct for v7 syndrome values | Peter Maydell | 2 | -5/+15 |
| 2018-10-24 | target/arm: New utility function to extract EC from syndrome | Peter Maydell | 4 | -4/+9 |
| 2018-10-24 | target/arm: Implement HCR.PTW | Peter Maydell | 1 | -1/+20 |
| 2018-10-24 | target/arm: Implement HCR.VI and VF | Peter Maydell | 1 | -4/+43 |
| 2018-10-24 | target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set | Peter Maydell | 1 | -4/+18 |
| 2018-10-24 | target/arm: Implement HCR.DC | Peter Maydell | 1 | -2/+21 |
| 2018-10-24 | target/arm: Implement HCR.FB | Peter Maydell | 1 | -72/+113 |
| 2018-10-24 | target/arm: Make switch_mode() file-local | Peter Maydell | 2 | -3/+4 |
| 2018-10-24 | target/arm: Improve debug logging of AArch32 exception return | Peter Maydell | 3 | -6/+29 |
| 2018-10-24 | target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test | Richard Henderson | 5 | -32/+49 |
| 2018-10-24 | target/arm: Convert sve from feature bit to aa64pfr0 test | Richard Henderson | 5 | -9/+28 |
| 2018-10-24 | target/arm: Convert jazelle from feature bit to isar1 test | Richard Henderson | 3 | -5/+20 |
| 2018-10-24 | target/arm: Convert division from feature bits to isar0 tests | Richard Henderson | 3 | -13/+13 |
