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2018-11-02target/arm: Conditionalize some asserts on aarch32 supportRichard Henderson2-2/+18
2018-11-02Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf1' in...Peter Maydell1-1/+1
2018-11-02Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-3.1-pull-request' ...Peter Maydell2-4/+3
2018-11-01Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20181031' into stagingPeter Maydell3-375/+355
2018-11-01target/m68k: use EXCP_ILLEGAL instead of EXCP_UNSUPPORTEDLaurent Vivier2-4/+3
2018-10-31decodetree: Remove "insn" argument from trans_* expandersRichard Henderson3-375/+355
2018-10-30i386: Add PKU on Skylake-Server CPU modelTao Xu1-0/+4
2018-10-30i386: Add new model of Cascadelake-ServerTao Xu1-0/+54
2018-10-30x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIESRobert Hoo3-1/+42
2018-10-30x86: Data structure changes to support MSR based featuresRobert Hoo1-55/+142
2018-10-30kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system ioctlRobert Hoo1-0/+80
2018-10-30target/i386: Remove #ifdeffed-out icebp debugging hackPeter Maydell1-6/+0
2018-10-30i386: correct cpu_x86_cpuid(0xd)Sebastian Andrzej Siewior1-1/+1
2018-10-30target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64Dayeol Lee1-1/+1
2018-10-29target/mips: Amend MXU ASE overview noteAleksandar Markovic1-10/+74
2018-10-29target/mips: Move MXU_EN check one level higherAleksandar Markovic1-271/+238
2018-10-29target/mips: Add emulation of MXU instructions S32LDD and S32LDDRCraig Janeczek1-7/+47
2018-10-29target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSUCraig Janeczek1-7/+94
2018-10-29target/mips: Add emulation of MXU instruction D16MACCraig Janeczek1-3/+87
2018-10-29target/mips: Add emulation of MXU instruction D16MULCraig Janeczek1-3/+63
2018-10-29target/mips: Add emulation of MXU instruction S8LDDCraig Janeczek1-3/+87
2018-10-29target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switchAleksandar Markovic1-18/+23
2018-10-29target/mips: Add emulation of MXU instructions S32I2M and S32M2ICraig Janeczek1-6/+85
2018-10-29target/mips: Add emulation of non-MXU MULL within MXU decoding engineCraig Janeczek1-1/+18
2018-10-29target/mips: Add bit encoding for MXU operand getting pattern 'optn3'Craig Janeczek1-0/+10
2018-10-29target/mips: Add bit encoding for MXU operand getting pattern 'optn2'Craig Janeczek1-0/+6
2018-10-29target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'Aleksandar Markovic1-0/+6
2018-10-29target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'Craig Janeczek1-0/+6
2018-10-29target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'Aleksandar Markovic1-0/+6
2018-10-29target/mips: Add MXU decoding engineAleksandar Markovic1-2/+1141
2018-10-29target/mips: Add and integrate MXU decoding engine placeholderAleksandar Markovic1-0/+8
2018-10-29target/mips: Amend MXU instruction opcodesAleksandar Markovic1-91/+69
2018-10-29target/mips: Define a bit for MXU in insn_flagsCraig Janeczek1-0/+1
2018-10-29target/mips: Introduce MXU registersCraig Janeczek2-0/+30
2018-10-29target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder casesAleksandar Markovic1-0/+2
2018-10-25target/mips: Add disassembler support for nanoMIPSAleksandar Markovic1-2/+11
2018-10-25target/mips: Implement emulation of nanoMIPS EVA instructionsDimitrije Nikolic1-0/+128
2018-10-25target/mips: Add nanoMIPS CRC32 instruction poolAleksandar Markovic1-0/+10
2018-10-25Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' in...Peter Maydell6-362/+420
2018-10-24Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-2018-part...Peter Maydell3-19/+908
2018-10-24target/mips: Fix decoding of ALIGN and DALIGN instructionsAleksandar Markovic1-8/+32
2018-10-24target/mips: Fix the title of translate.cAleksandar Markovic1-1/+1
2018-10-24target/mips: Define the R5900 CPUFredrik Noring1-0/+59
2018-10-24target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user onlyFredrik Noring1-1/+22
2018-10-24target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IVFredrik Noring1-2/+3
2018-10-24target/mips: Support R5900 DIV1 and DIVU1 instructionsFredrik Noring1-3/+9
2018-10-24target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructionsFredrik Noring1-6/+17
2018-10-24target/mips: Support R5900 three-operand MULT1 and MULTU1 instructionsFredrik Noring1-3/+14
2018-10-24target/mips: Support R5900 three-operand MULT and MULTU instructionsFredrik Noring1-0/+74
2018-10-24target/mips: Add a placeholder for R5900 MMI3 instruction subclassFredrik Noring1-1/+30