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2018-11-02
target/arm: Conditionalize some asserts on aarch32 support
Richard Henderson
2
-2
/
+18
2018-11-02
Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf1' in...
Peter Maydell
1
-1
/
+1
2018-11-02
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-3.1-pull-request' ...
Peter Maydell
2
-4
/
+3
2018-11-01
Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20181031' into staging
Peter Maydell
3
-375
/
+355
2018-11-01
target/m68k: use EXCP_ILLEGAL instead of EXCP_UNSUPPORTED
Laurent Vivier
2
-4
/
+3
2018-10-31
decodetree: Remove "insn" argument from trans_* expanders
Richard Henderson
3
-375
/
+355
2018-10-30
i386: Add PKU on Skylake-Server CPU model
Tao Xu
1
-0
/
+4
2018-10-30
i386: Add new model of Cascadelake-Server
Tao Xu
1
-0
/
+54
2018-10-30
x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES
Robert Hoo
3
-1
/
+42
2018-10-30
x86: Data structure changes to support MSR based features
Robert Hoo
1
-55
/
+142
2018-10-30
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system ioctl
Robert Hoo
1
-0
/
+80
2018-10-30
target/i386: Remove #ifdeffed-out icebp debugging hack
Peter Maydell
1
-6
/
+0
2018-10-30
i386: correct cpu_x86_cpuid(0xd)
Sebastian Andrzej Siewior
1
-1
/
+1
2018-10-30
target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
Dayeol Lee
1
-1
/
+1
2018-10-29
target/mips: Amend MXU ASE overview note
Aleksandar Markovic
1
-10
/
+74
2018-10-29
target/mips: Move MXU_EN check one level higher
Aleksandar Markovic
1
-271
/
+238
2018-10-29
target/mips: Add emulation of MXU instructions S32LDD and S32LDDR
Craig Janeczek
1
-7
/
+47
2018-10-29
target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU
Craig Janeczek
1
-7
/
+94
2018-10-29
target/mips: Add emulation of MXU instruction D16MAC
Craig Janeczek
1
-3
/
+87
2018-10-29
target/mips: Add emulation of MXU instruction D16MUL
Craig Janeczek
1
-3
/
+63
2018-10-29
target/mips: Add emulation of MXU instruction S8LDD
Craig Janeczek
1
-3
/
+87
2018-10-29
target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch
Aleksandar Markovic
1
-18
/
+23
2018-10-29
target/mips: Add emulation of MXU instructions S32I2M and S32M2I
Craig Janeczek
1
-6
/
+85
2018-10-29
target/mips: Add emulation of non-MXU MULL within MXU decoding engine
Craig Janeczek
1
-1
/
+18
2018-10-29
target/mips: Add bit encoding for MXU operand getting pattern 'optn3'
Craig Janeczek
1
-0
/
+10
2018-10-29
target/mips: Add bit encoding for MXU operand getting pattern 'optn2'
Craig Janeczek
1
-0
/
+6
2018-10-29
target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'
Aleksandar Markovic
1
-0
/
+6
2018-10-29
target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'
Craig Janeczek
1
-0
/
+6
2018-10-29
target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'
Aleksandar Markovic
1
-0
/
+6
2018-10-29
target/mips: Add MXU decoding engine
Aleksandar Markovic
1
-2
/
+1141
2018-10-29
target/mips: Add and integrate MXU decoding engine placeholder
Aleksandar Markovic
1
-0
/
+8
2018-10-29
target/mips: Amend MXU instruction opcodes
Aleksandar Markovic
1
-91
/
+69
2018-10-29
target/mips: Define a bit for MXU in insn_flags
Craig Janeczek
1
-0
/
+1
2018-10-29
target/mips: Introduce MXU registers
Craig Janeczek
2
-0
/
+30
2018-10-29
target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases
Aleksandar Markovic
1
-0
/
+2
2018-10-25
target/mips: Add disassembler support for nanoMIPS
Aleksandar Markovic
1
-2
/
+11
2018-10-25
target/mips: Implement emulation of nanoMIPS EVA instructions
Dimitrije Nikolic
1
-0
/
+128
2018-10-25
target/mips: Add nanoMIPS CRC32 instruction pool
Aleksandar Markovic
1
-0
/
+10
2018-10-25
Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' in...
Peter Maydell
6
-362
/
+420
2018-10-24
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-2018-part...
Peter Maydell
3
-19
/
+908
2018-10-24
target/mips: Fix decoding of ALIGN and DALIGN instructions
Aleksandar Markovic
1
-8
/
+32
2018-10-24
target/mips: Fix the title of translate.c
Aleksandar Markovic
1
-1
/
+1
2018-10-24
target/mips: Define the R5900 CPU
Fredrik Noring
1
-0
/
+59
2018-10-24
target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only
Fredrik Noring
1
-1
/
+22
2018-10-24
target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV
Fredrik Noring
1
-2
/
+3
2018-10-24
target/mips: Support R5900 DIV1 and DIVU1 instructions
Fredrik Noring
1
-3
/
+9
2018-10-24
target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions
Fredrik Noring
1
-6
/
+17
2018-10-24
target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions
Fredrik Noring
1
-3
/
+14
2018-10-24
target/mips: Support R5900 three-operand MULT and MULTU instructions
Fredrik Noring
1
-0
/
+74
2018-10-24
target/mips: Add a placeholder for R5900 MMI3 instruction subclass
Fredrik Noring
1
-1
/
+30
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