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2021-06-16target/arm: Fix mte page crossing testRichard Henderson1-1/+1
2021-06-15target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16Richard Henderson1-30/+48
2021-06-15target/arm: Remove fprintf from disas_simd_mod_immRichard Henderson1-1/+0
2021-06-15target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16Richard Henderson1-2/+2
2021-06-08Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...Peter Maydell13-104/+1028
2021-06-08target/riscv: rvb: add b-ext version cpu optionFrank Chang2-0/+26
2021-06-08target/riscv: rvb: support and turn on B-extension from command lineKito Cheng2-0/+5
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng3-0/+35
2021-06-08target/riscv: rvb: address calculationKito Cheng3-0/+62
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang5-0/+64
2021-06-08target/riscv: rvb: generalized reverseFrank Chang6-0/+132
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng3-0/+81
2021-06-08target/riscv: rvb: shift onesKito Cheng3-0/+74
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang3-0/+175
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang2-50/+43
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng2-0/+15
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng2-0/+28
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng3-0/+78
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng2-0/+21
2021-06-08target/riscv: rvb: count bits setFrank Chang3-0/+21
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng4-1/+93
2021-06-08target/riscv: reformat @sh format encoding for B-extensionKito Cheng1-5/+5
2021-06-08target/riscv: Pass the same value to oprsz and maxsz.LIU Zhiwei1-39/+50
2021-06-08target/riscv/pmp: Add assert for ePMP operationsAlistair Francis1-0/+4
2021-06-08target/riscv: Dump CSR mscratch/sscratch/satpChangbin Du1-2/+5
2021-06-08target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng2-4/+2
2021-06-08target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé1-0/+2
2021-06-08target/riscv: fix wfi exception behaviorJose Martins2-3/+9
2021-06-05target/mips: Fix 'Uncoditional' typoPhilippe Mathieu-Daudé1-3/+3
2021-06-05target/hppa: Remove unused 'memory.h' headerPhilippe Mathieu-Daudé1-1/+0
2021-06-05target/nios2: fix page-fit instruction countPavel Dovgalyuk1-1/+1
2021-06-05target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé1-0/+2
2021-06-04i386: run accel_cpu_instance_init as post_initClaudio Fontana1-3/+7
2021-06-04i386: reorder call to cpu_exec_realizefnClaudio Fontana2-30/+61
2021-06-04target/i386: Fix decode of cr8Richard Henderson1-0/+1
2021-06-04target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versaPaolo Bonzini1-1/+1
2021-06-04target/i386: tcg: fix loading of registers from 16-bit TSSPaolo Bonzini1-14/+11
2021-06-04target/i386: tcg: fix segment register offsets for 16-bit TSSPaolo Bonzini1-2/+2
2021-06-03softfloat: Introduce Floatx80RoundPrecRichard Henderson3-93/+126
2021-06-03hvf: Simplify post reset/init/loadvm hooksAlexander Graf1-1/+4
2021-06-03hvf: Introduce hvf vcpu structAlexander Graf8-234/+236
2021-06-03hvf: Remove hvf-accel-ops.hAlexander Graf1-2/+0
2021-06-03hvf: Use cpu_synchronize_state()Alexander Graf1-5/+4
2021-06-03hvf: Split out common code on vcpu init and destroyAlexander Graf1-21/+2
2021-06-03hvf: Move hvf internal definitions into common headerAlexander Graf1-30/+1
2021-06-03hvf: Move cpu functions into common directoryAlexander Graf3-306/+0
2021-06-03hvf: Move vcpu thread functions into common directoryAlexander Graf4-171/+1
2021-06-03hvf: Move assert_hvf_ok() into common directoryAlexander Graf1-32/+1
2021-06-03target/arm: Enable BFloat16 extensionsRichard Henderson3-0/+7
2021-06-03target/arm: Implement bfloat widening fma (indexed)Richard Henderson7-1/+82