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2023-05-05target/riscv: Hoist second stage mode change to callersRichard Henderson1-10/+2
2023-05-05target/riscv: Check SUM in the correct registerRichard Henderson2-5/+13
2023-05-05target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_indexRichard Henderson2-37/+18
2023-05-05target/riscv: Move hstatus.spvp check to check_access_hlsvRichard Henderson2-10/+2
2023-05-05target/riscv: Introduce mmuidx_2stageRichard Henderson3-15/+11
2023-05-05target/riscv: Introduce mmuidx_privRichard Henderson2-5/+10
2023-05-05target/riscv: Introduce mmuidx_sumRichard Henderson2-1/+6
2023-05-05target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BITRichard Henderson3-4/+6
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson6-109/+165
2023-05-05target/riscv: Use cpu_ld*_code_mmu for HLVXRichard Henderson1-2/+11
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu6-10/+35
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu5-16/+8
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei4-9/+11
2023-05-05target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson3-48/+33
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei5-36/+32
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei4-16/+20
2023-05-05target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei3-9/+4
2023-05-05target/riscv: fix H extension TVM trapYi Chen2-27/+41
2023-05-05target/riscv: Use check for relationship between Zdinx/Zhinx{min} and ZfinxWeiwei Li1-2/+3
2023-05-05target/riscv: Legalize MPP value in write_mstatusWeiwei Li2-6/+34
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li5-5/+5
2023-05-05target/riscv: Fix the mstatus.MPP value after executing MRETWeiwei Li1-1/+2
2023-05-05target/riscv/cpu.c: redesign register_cpu_props()Daniel Henrique Barboza2-35/+11
2023-05-05target/riscv: add RVG and remove cpu->cfg.ext_gDaniel Henrique Barboza2-10/+9
2023-05-05target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()Daniel Henrique Barboza1-2/+1
2023-05-05target/riscv: remove riscv_cpu_sync_misa_cfg()Daniel Henrique Barboza1-52/+0
2023-05-05target/riscv: remove cpu->cfg.ext_vDaniel Henrique Barboza2-8/+5
2023-05-05target/riscv: remove cpu->cfg.ext_jDaniel Henrique Barboza2-4/+3
2023-05-05target/riscv: remove cpu->cfg.ext_hDaniel Henrique Barboza2-6/+5
2023-05-05target/riscv: remove cpu->cfg.ext_uDaniel Henrique Barboza2-6/+4
2023-05-05target/riscv: remove cpu->cfg.ext_sDaniel Henrique Barboza2-7/+5
2023-05-05target/riscv: remove cpu->cfg.ext_mDaniel Henrique Barboza2-6/+5
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza3-7/+6
2023-05-05target/riscv: remove cpu->cfg.ext_iDaniel Henrique Barboza2-9/+7
2023-05-05target/riscv: remove cpu->cfg.ext_fDaniel Henrique Barboza2-14/+13
2023-05-05target/riscv: remove cpu->cfg.ext_dDaniel Henrique Barboza2-10/+8
2023-05-05target/riscv: remove cpu->cfg.ext_cDaniel Henrique Barboza2-6/+4
2023-05-05target/riscv: remove cpu->cfg.ext_aDaniel Henrique Barboza2-9/+8
2023-05-05target/riscv: introduce riscv_cpu_add_misa_properties()Daniel Henrique Barboza1-0/+65
2023-05-05target/riscv/cpu.c: remove 'multi_letter' from isa_ext_dataDaniel Henrique Barboza1-67/+65
2023-05-05target/riscv: remove MISA properties from isa_edata_arr[]Daniel Henrique Barboza1-2/+17
2023-05-05target/riscv: sync env->misa_ext* with cpu->cfg in realize()Daniel Henrique Barboza1-38/+56
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li9-56/+91
2023-05-05target/riscv: Fix format for commentsWeiwei Li11-104/+151
2023-05-05target/riscv: Fix format for indentationWeiwei Li12-241/+247
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li8-70/+64
2023-05-05target/riscv: Set opcode to env->bins for illegal/virtual instruction faultWeiwei Li1-0/+2
2023-05-05target/riscv: Fix addr type for get_physical_addressWeiwei Li1-2/+2
2023-05-05target/riscv: Remove redundant parenthesesWeiwei Li1-1/+1
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei5-12/+9
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