aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)AuthorFilesLines
2021-09-16target/i386: spelling: occured=>occurred, mininum=>minimumMichael Tokarev1-1/+1
2021-09-13Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210913-...Peter Maydell9-108/+156
2021-09-13target/arm: Merge disas_a64_insn into aarch64_tr_translate_insnRichard Henderson1-115/+109
2021-09-13target/arm: Take an exception if PSTATE.IL is setPeter Maydell7-0/+49
2021-09-13hw/arm/virt: add ITS support in virt GICShashi Mallela1-2/+2
2021-09-13hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VMMarc Zyngier1-1/+6
2021-09-13Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell9-56/+169
2021-09-13Fix nvmm_ram_block_added() function argumentsReinoud Zandijk1-2/+3
2021-09-13target/i386: Added vVMLOAD and vVMSAVE featureLara Lazier4-1/+34
2021-09-13target/i386: Added changed priority check for VIRQLara Lazier3-15/+22
2021-09-13target/i386: Added ignore TPR check in ctl_has_irqLara Lazier1-0/+5
2021-09-13target/i386: Added VGIF V_IRQ masking capabilityLara Lazier3-2/+19
2021-09-13target/i386: Moved int_ctl into CPUX86State structureLara Lazier6-38/+41
2021-09-13target/i386: Added VGIF featureLara Lazier3-3/+37
2021-09-13target/i386: VMRUN and VMLOAD canonicalizationsLara Lazier3-18/+30
2021-09-13target/i386: add missing bits to CR4_RESERVED_MASKDaniel P. Berrangé1-0/+1
2021-09-08target/sparc: Drop use of gen_io_end()Peter Maydell1-15/+10
2021-09-07s390x/cpumodel: Add more feature to gen16 default modelChristian Borntraeger1-1/+7
2021-09-06hw/s390x/s390-skeys: lazy storage key enablement under TCGDavid Hildenbrand2-0/+17
2021-09-06s390x/mmu_helper: avoid setting the storage key if nothing changedDavid Hildenbrand1-4/+7
2021-09-06s390x/mmu_helper: move address validation into mmu_translate*()David Hildenbrand4-29/+24
2021-09-06s390x/mmu_helper: fixup mmu_translate() documentationDavid Hildenbrand1-1/+2
2021-09-06s390x/mmu_helper: no need to pass access type to mmu_translate_asce()David Hildenbrand1-2/+2
2021-09-06s390x/tcg: check for addressing exceptions for RRBE, SSKE and ISKEDavid Hildenbrand4-16/+35
2021-09-06s390x/tcg: convert real to absolute address for RRBE, SSKE and ISKEDavid Hildenbrand1-0/+3
2021-09-06s390x/tcg: fix ignoring bit 63 when setting the storage key in SSKEDavid Hildenbrand1-1/+1
2021-09-06s390x/tcg: wrap address for RRBEDavid Hildenbrand1-3/+4
2021-09-06s390x/ioinst: Fix wrong MSCH alignment check on little endianDavid Hildenbrand1-1/+1
2021-09-06s390x/tcg: fix and optimize SPX (SET PREFIX)David Hildenbrand1-1/+14
2021-09-01target-arm: Add support for Fujitsu A64FXShuuichirou Ishii1-0/+48
2021-09-01target/arm: Enable MVE in Cortex-M55Peter Maydell1-5/+2
2021-09-01target/arm: Implement MVE VRINT insnsPeter Maydell4-0/+93
2021-09-01target/arm: Implement MVE VCVT between single and half precisionPeter Maydell4-0/+108
2021-09-01target/arm: Implement MVE VCVT with specified rounding modePeter Maydell4-0/+105
2021-09-01target/arm: Implement MVE VCVT between fp and integerPeter Maydell2-0/+39
2021-09-01target/arm: Implement MVE VCVT between floating and fixed pointPeter Maydell4-0/+82
2021-09-01target/arm: Implement MVE fp scalar comparisonsPeter Maydell4-24/+131
2021-09-01target/arm: Implement MVE fp vector comparisonsPeter Maydell4-6/+137
2021-09-01target/arm: Implement MVE FP max/min across vectorPeter Maydell4-6/+102
2021-09-01target/arm: Implement MVE fp-with-scalar VFMA, VFMASPeter Maydell4-3/+56
2021-09-01target/arm: Implement MVE scalar fp insnsPeter Maydell4-6/+85
2021-09-01target/arm: Implement MVE VMAXNMA and VMINNMAPeter Maydell4-0/+42
2021-09-01target/arm: Implement MVE VCMUL and VCMLAPeter Maydell4-8/+139
2021-09-01target/arm: Implement MVE VFMA and VFMSPeter Maydell4-0/+48
2021-09-01target/arm: Implement MVE VCADDPeter Maydell4-1/+57
2021-09-01target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNMPeter Maydell4-0/+42
2021-09-01target/arm: Implement MVE VADD (floating-point)Peter Maydell6-6/+76
2021-09-01target/riscv: Use {get,dest}_gpr for RVVRichard Henderson2-61/+26
2021-09-01target/riscv: Tidy trans_rvh.c.incRichard Henderson2-210/+57
2021-09-01target/riscv: Use {get,dest}_gpr for RVDRichard Henderson1-65/+60