| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-05-05 | target/sparc: Use MO_ALIGN where required | Richard Henderson | 1 | -32/+34 |
| 2023-05-05 | target/hppa: Use MO_ALIGN for system UNALIGN() | Richard Henderson | 1 | -1/+1 |
| 2023-05-05 | target/alpha: Use MO_ALIGN where required | Richard Henderson | 1 | -16/+20 |
| 2023-05-05 | target/alpha: Use MO_ALIGN for system UNALIGN() | Richard Henderson | 1 | -1/+1 |
| 2023-05-05 | target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_* | Richard Henderson | 1 | -2/+2 |
| 2023-05-05 | target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_* | Richard Henderson | 1 | -15/+28 |
| 2023-05-05 | target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_* | Richard Henderson | 1 | -81/+71 |
| 2023-05-05 | target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_* | Richard Henderson | 2 | -5/+5 |
| 2023-05-05 | target/m68k: Finish conversion to tcg_gen_qemu_{ld,st}_* | Richard Henderson | 1 | -51/+25 |
| 2023-05-05 | target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_* | Richard Henderson | 4 | -42/+40 |
| 2023-05-05 | target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_* | Richard Henderson | 1 | -14/+4 |
| 2023-05-05 | target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_* | Richard Henderson | 1 | -8/+8 |
| 2023-05-05 | target/riscv: add Ventana's Veyron V1 CPU | Rahul Pathak | 3 | -0/+43 |
| 2023-05-05 | riscv: Make sure an exception is raised if a pte is malformed | Alexandre Ghiti | 2 | -4/+12 |
| 2023-05-05 | target/riscv: Fix Guest Physical Address Translation | Irina Ryapolova | 1 | -9/+16 |
| 2023-05-05 | target/riscv: Restore the predicate() NULL check behavior | Bin Meng | 1 | -2/+9 |
| 2023-05-05 | target/riscv: add TYPE_RISCV_DYNAMIC_CPU | Daniel Henrique Barboza | 3 | -5/+21 |
| 2023-05-05 | target/riscv: add query-cpy-definitions support | Daniel Henrique Barboza | 2 | -1/+55 |
| 2023-05-05 | target/riscv: add CPU QOM header | Daniel Henrique Barboza | 2 | -45/+71 |
| 2023-05-05 | target/riscv: Reorg sum check in get_physical_address | Richard Henderson | 1 | -11/+11 |
| 2023-05-05 | target/riscv: Reorg access check in get_physical_address | Richard Henderson | 1 | -33/+36 |
| 2023-05-05 | target/riscv: Merge checks for reserved pte flags | Richard Henderson | 1 | -6/+6 |
| 2023-05-05 | target/riscv: Don't modify SUM with is_debug | Richard Henderson | 1 | -1/+1 |
| 2023-05-05 | target/riscv: Suppress pte update with is_debug | Richard Henderson | 1 | -1/+1 |
| 2023-05-05 | target/riscv: Move leaf pte processing out of level loop | Richard Henderson | 1 | -111/+123 |
| 2023-05-05 | target/riscv: Hoist pbmte and hade out of the level loop | Richard Henderson | 1 | -8/+8 |
| 2023-05-05 | target/riscv: Hoist second stage mode change to callers | Richard Henderson | 1 | -10/+2 |
| 2023-05-05 | target/riscv: Check SUM in the correct register | Richard Henderson | 2 | -5/+13 |
| 2023-05-05 | target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index | Richard Henderson | 2 | -37/+18 |
| 2023-05-05 | target/riscv: Move hstatus.spvp check to check_access_hlsv | Richard Henderson | 2 | -10/+2 |
| 2023-05-05 | target/riscv: Introduce mmuidx_2stage | Richard Henderson | 3 | -15/+11 |
| 2023-05-05 | target/riscv: Introduce mmuidx_priv | Richard Henderson | 2 | -5/+10 |
| 2023-05-05 | target/riscv: Introduce mmuidx_sum | Richard Henderson | 2 | -1/+6 |
| 2023-05-05 | target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT | Richard Henderson | 3 | -4/+6 |
| 2023-05-05 | target/riscv: Handle HLV, HSV via helpers | Richard Henderson | 6 | -109/+165 |
| 2023-05-05 | target/riscv: Use cpu_ld*_code_mmu for HLVX | Richard Henderson | 1 | -2/+11 |
| 2023-05-05 | target/riscv: Reduce overhead of MSTATUS_SUM change | Fei Wu | 6 | -10/+35 |
| 2023-05-05 | target/riscv: Separate priv from mmu_idx | Fei Wu | 5 | -16/+8 |
| 2023-05-05 | target/riscv: Add a tb flags field for vstart | LIU Zhiwei | 4 | -9/+11 |
| 2023-05-05 | target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags | Richard Henderson | 3 | -48/+33 |
| 2023-05-05 | target/riscv: Encode the FS and VS on a normal way for tb flags | LIU Zhiwei | 5 | -36/+32 |
| 2023-05-05 | target/riscv: Add a general status enum for extensions | LIU Zhiwei | 4 | -16/+20 |
| 2023-05-05 | target/riscv: Extract virt enabled state from tb flags | LIU Zhiwei | 3 | -9/+4 |
| 2023-05-05 | target/riscv: fix H extension TVM trap | Yi Chen | 2 | -27/+41 |
| 2023-05-05 | target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx | Weiwei Li | 1 | -2/+3 |
| 2023-05-05 | target/riscv: Legalize MPP value in write_mstatus | Weiwei Li | 2 | -6/+34 |
| 2023-05-05 | target/riscv: Use PRV_RESERVED instead of PRV_H | Weiwei Li | 5 | -5/+5 |
| 2023-05-05 | target/riscv: Fix the mstatus.MPP value after executing MRET | Weiwei Li | 1 | -1/+2 |
| 2023-05-05 | target/riscv/cpu.c: redesign register_cpu_props() | Daniel Henrique Barboza | 2 | -35/+11 |
| 2023-05-05 | target/riscv: add RVG and remove cpu->cfg.ext_g | Daniel Henrique Barboza | 2 | -10/+9 |
