riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-06-21	i386/kvm: convert hyperv enlightenments properties from bools to bits	Vitaly Kuznetsov	5	-79/+89
2019-06-21	hax: Honor CPUState::halted	Colin Xu	1	-2/+34
2019-06-18	target/arm: Check for dp support for dp VFM, not sp	Peter Maydell	1	-4/+4
2019-06-17	target/arm: Only implement doubles if the FPU supports them	Peter Maydell	2	-0/+90
2019-06-17	target/arm: Fix typos in trans function prototypes	Peter Maydell	1	-14/+14
2019-06-17	target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d	Peter Maydell	1	-10/+2
2019-06-17	target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16	Peter Maydell	1	-15/+11
2019-06-17	target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32	Peter Maydell	1	-15/+12
2019-06-17	target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops	Peter Maydell	1	-34/+28
2019-06-17	target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT	Peter Maydell	1	-60/+22
2019-06-17	target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F	Peter Maydell	1	-3/+3
2019-06-17	target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US]	Peter Maydell	1	-4/+3
2019-06-17	target/arm: Stop using cpu_F0s for NEON_2RM_VRINT*	Peter Maydell	1	-5/+3
2019-06-17	target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F	Peter Maydell	1	-11/+2
2019-06-17	target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F	Peter Maydell	1	-11/+8
2019-06-17	target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm	Peter Maydell	2	-28/+10
2019-06-17	target/arm: Move vfp_expand_imm() to translate.[ch]	Peter Maydell	4	-33/+40
2019-06-17	target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property	Peter Maydell	2	-0/+31
2019-06-17	target/arm: Allow VFP and Neon to be disabled via a CPU property	Peter Maydell	2	-6/+148
2019-06-13	target/arm: Fix short-vector increment behaviour	Peter Maydell	1	-40/+60
2019-06-13	target/arm: Convert float-to-integer VCVT insns to decodetree	Peter Maydell	3	-239/+80
2019-06-13	target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree	Peter Maydell	3	-55/+136
2019-06-13	target/arm: Convert VJCVT to decodetree	Peter Maydell	3	-11/+33
2019-06-13	target/arm: Convert integer-to-float insns to decodetree	Peter Maydell	3	-11/+65
2019-06-13	target/arm: Convert double-single precision conversion insns to decodetree	Peter Maydell	3	-12/+55
2019-06-13	target/arm: Convert VFP round insns to decodetree	Peter Maydell	3	-44/+179
2019-06-13	target/arm: Convert the VCVT-to-f16 insns to decodetree	Peter Maydell	3	-78/+69
2019-06-13	target/arm: Convert the VCVT-from-f16 insns to decodetree	Peter Maydell	3	-55/+89
2019-06-13	target/arm: Convert VFP comparison insns to decodetree	Peter Maydell	3	-50/+81
2019-06-13	target/arm: Convert VMOV (register) to decodetree	Peter Maydell	3	-7/+16
2019-06-13	target/arm: Convert VSQRT to decodetree	Peter Maydell	3	-13/+26
2019-06-13	target/arm: Convert VNEG to decodetree	Peter Maydell	3	-5/+16
2019-06-13	target/arm: Convert VABS to decodetree	Peter Maydell	3	-4/+180
2019-06-13	target/arm: Convert VMOV (imm) to decodetree	Peter Maydell	3	-25/+136
2019-06-13	target/arm: Convert VFP fused multiply-add insns to decodetree	Peter Maydell	3	-52/+131
2019-06-13	target/arm: Convert VDIV to decodetree	Peter Maydell	3	-20/+16
2019-06-13	target/arm: Convert VSUB to decodetree	Peter Maydell	3	-5/+16
2019-06-13	target/arm: Convert VADD to decodetree	Peter Maydell	3	-5/+16
2019-06-13	target/arm: Convert VNMUL to decodetree	Peter Maydell	3	-6/+30
2019-06-13	target/arm: Convert VMUL to decodetree	Peter Maydell	3	-4/+16
2019-06-13	target/arm: Convert VFP VNMLA to decodetree	Peter Maydell	3	-18/+40
2019-06-13	target/arm: Convert VFP VNMLS to decodetree	Peter Maydell	3	-23/+48
2019-06-13	target/arm: Convert VFP VMLS to decodetree	Peter Maydell	3	-7/+44
2019-06-13	target/arm: Convert VFP VMLA to decodetree	Peter Maydell	4	-6/+224
2019-06-13	target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d	Peter Maydell	2	-36/+28
2019-06-13	target/arm: Convert the VFP load/store multiple insns to decodetree	Peter Maydell	3	-94/+183
2019-06-13	target/arm: Convert VFP VLDR and VSTR to decodetree	Peter Maydell	3	-20/+82
2019-06-13	target/arm: Convert VFP two-register transfer insns to decodetree	Peter Maydell	3	-44/+77
2019-06-13	target/arm: Convert "single-precision" register moves to decodetree	Peter Maydell	3	-145/+168
2019-06-13	target/arm: Convert "double-precision" register moves to decodetree	Peter Maydell	3	-81/+185