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2020-07-10target/i386: Add SERIALIZE cpu featureCathy Zhang2-1/+3
2020-07-10target/i386: Correct the warning message of Intel PTLuwei Kang1-1/+1
2020-07-10target/i386: sev: fail query-sev-capabilities if QEMU cannot use SEVPaolo Bonzini1-0/+9
2020-07-10target/i386: sev: provide proper error reporting for query-sev-capabilitiesPaolo Bonzini4-20/+13
2020-07-10KVM: x86: believe what KVM says about WAITPKGPaolo Bonzini3-6/+9
2020-07-10target/i386: implement undocumented "smsw r32" behaviorPaolo Bonzini1-6/+7
2020-07-10target/i386: remove gen_io_endPaolo Bonzini1-13/+9
2020-07-10i386: hvf: Clean up synchronize functionsRoman Bolshakov1-20/+16
2020-07-10i386: hvf: Don't duplicate register resetRoman Bolshakov2-92/+0
2020-07-10i386: hvf: Move Guest LMA reset to macvm_set_cr0()Roman Bolshakov2-1/+4
2020-07-10i386: hvf: Make long mode enter and exit clearerCameron Esfahani1-5/+7
2020-07-10i386: hvf: Add hvf_cpu_synchronize_pre_loadvm()Roman Bolshakov1-0/+11
2020-07-10i386: hvf: Set env->eip in macvm_set_rip()Roman Bolshakov1-0/+1
2020-07-10KVM: add support for AMD nested live migrationPaolo Bonzini4-9/+70
2020-07-10target/i386: fix IEEE SSE floating-point exception raisingJoseph Myers9-12/+82
2020-07-10target/i386: set SSE FTZ in correct floating-point stateJoseph Myers1-1/+1
2020-07-10tcg/svm: use host cr4 during NPT page table walkAlexander Boettcher3-3/+9
2020-07-10target/avr: Add definitions of AVR core typesMichael Rolnik1-0/+151
2020-07-10target/avr: Introduce enumeration AVRFeatureMichael Rolnik1-0/+46
2020-07-10target/avr: CPU class: Add GDB supportMichael Rolnik3-0/+90
2020-07-10target/avr: CPU class: Add migration supportMichael Rolnik3-0/+122
2020-07-10target/avr: CPU class: Add memory management supportMichael Rolnik2-0/+53
2020-07-10target/avr: CPU class: Add interrupt handling supportMichael Rolnik2-0/+91
2020-07-10target/avr: Introduce basic CPU class objectMichael Rolnik3-0/+399
2020-07-10target/avr: Add basic parameters of the new platformMichael Rolnik2-0/+102
2020-07-10error: Eliminate error_propagate() manuallyMarkus Armbruster1-14/+5
2020-07-10error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster6-40/+14
2020-07-10qom: Use returned bool to check for failure, Coccinelle partMarkus Armbruster3-11/+6
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster4-33/+30
2020-07-10qapi: Use returned bool to check for failure, Coccinelle partMarkus Armbruster6-28/+14
2020-07-08Merge remote-tracking branch 'remotes/vivier/tags/m68k-next-pull-request' int...Peter Maydell1-9/+8
2020-07-07Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell1-0/+7
2020-07-06target/m68k: consolidate physical translation offset into get_physical_address()Mark Cave-Ayland1-11/+6
2020-07-06target/m68k: fix physical address translation in m68k_cpu_get_phys_page_debug()Mark Cave-Ayland1-0/+4
2020-07-06Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...Peter Maydell1-0/+2
2020-07-04Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200703'...Peter Maydell8-6/+184
2020-07-04Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200703' into stagingPeter Maydell1-1/+1
2020-07-03target/arm: Fix temp double-free in sve ldr/strRichard Henderson3-6/+9
2020-07-03target/arm: kvm: Handle misconfigured dabt injectionBeata Michalska5-1/+124
2020-07-03target/arm: kvm: Handle DABT with no valid ISSBeata Michalska1-0/+52
2020-07-03target/s390x: Fix SQXBRRichard Henderson1-1/+1
2020-07-02target/riscv: configure and turn on vector extension from command lineLIU Zhiwei2-1/+46
2020-07-02target/riscv: vector compress instructionLIU Zhiwei4-0/+64
2020-07-02target/riscv: vector register gather instructionLIU Zhiwei4-0/+150
2020-07-02target/riscv: vector slide instructionsLIU Zhiwei4-0/+155
2020-07-02target/riscv: floating-point scalar move instructionsLIU Zhiwei2-0/+52
2020-07-02target/riscv: integer scalar move instructionLIU Zhiwei3-0/+67
2020-07-02target/riscv: integer extract instructionLIU Zhiwei2-0/+117
2020-07-02target/riscv: vector element index instructionLIU Zhiwei4-0/+56
2020-07-02target/riscv: vector iota instructionLIU Zhiwei4-0/+62