riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-06-03	hvf: Simplify post reset/init/loadvm hooks	Alexander Graf	1	-1/+4
2021-06-03	hvf: Introduce hvf vcpu struct	Alexander Graf	8	-234/+236
2021-06-03	hvf: Remove hvf-accel-ops.h	Alexander Graf	1	-2/+0
2021-06-03	hvf: Use cpu_synchronize_state()	Alexander Graf	1	-5/+4
2021-06-03	hvf: Split out common code on vcpu init and destroy	Alexander Graf	1	-21/+2
2021-06-03	hvf: Move hvf internal definitions into common header	Alexander Graf	1	-30/+1
2021-06-03	hvf: Move cpu functions into common directory	Alexander Graf	3	-306/+0
2021-06-03	hvf: Move vcpu thread functions into common directory	Alexander Graf	4	-171/+1
2021-06-03	hvf: Move assert_hvf_ok() into common directory	Alexander Graf	1	-32/+1
2021-06-03	target/arm: Enable BFloat16 extensions	Richard Henderson	3	-0/+7
2021-06-03	target/arm: Implement bfloat widening fma (indexed)	Richard Henderson	7	-1/+82
2021-06-03	target/arm: Implement bfloat widening fma (vector)	Richard Henderson	7	-4/+73
2021-06-03	target/arm: Implement bfloat16 matrix multiply accumulate	Richard Henderson	7	-3/+81
2021-06-03	target/arm: Implement bfloat16 dot product (indexed)	Richard Henderson	7	-9/+80
2021-06-03	target/arm: Implement bfloat16 dot product (vector)	Richard Henderson	7	-0/+89
2021-06-03	target/arm: Implement vector float32 to bfloat16 conversion	Richard Henderson	9	-0/+95
2021-06-03	target/arm: Implement scalar float32 to bfloat16 conversion	Richard Henderson	5	-0/+51
2021-06-03	target/arm: Unify unallocated path in disas_fp_1src	Richard Henderson	1	-9/+6
2021-06-03	target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16	Richard Henderson	1	-0/+15
2021-06-03	target/arm: use raise_exception_ra for stack limit exception	Jamie Iles	2	-10/+4
2021-06-03	target/arm: use raise_exception_ra for MTE check failure	Jamie Iles	1	-9/+3
2021-06-03	target/arm: fold do_raise_exception into raise_exception	Jamie Iles	1	-10/+2
2021-06-03	target/arm: fix missing exception class	Jamie Iles	1	-2/+9
2021-06-03	target/arm: Mark LDS{MIN,MAX} as signed operations	Richard Henderson	1	-3/+10
2021-06-03	target/arm: Allow board models to specify initial NS VTOR	Peter Maydell	2	-0/+12
2021-06-03	target/arm: Make FPSCR.LTPSIZE writable for MVE	Peter Maydell	3	-4/+9
2021-06-03	target/arm: Implement M-profile VPR register	Peter Maydell	3	-0/+63
2021-06-03	target/arm: Fix return values in fp_sysreg_checks()	Peter Maydell	1	-3/+3
2021-06-03	target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp	Peter Maydell	1	-2/+13
2021-06-03	target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp	Peter Maydell	1	-18/+19
2021-06-03	target/arm: Update feature checks for insns which are "MVE or FP"	Peter Maydell	1	-19/+29
2021-06-03	target/arm: Add isar feature check functions for MVE	Peter Maydell	1	-0/+22
2021-06-03	target/ppc: fix single-step exception regression	Luis Pires	1	-3/+2
2021-06-03	target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree	Matheus Ferst	3	-52/+45
2021-06-03	target/ppc: Move addpcis to decodetree	Matheus Ferst	3	-9/+13
2021-06-03	target/ppc: Implement vcfuged instruction	Matheus Ferst	3	-0/+64
2021-06-03	target/ppc: Implement cfuged instruction	Matheus Ferst	4	-0/+79
2021-06-03	target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions	Matheus Ferst	2	-0/+33
2021-06-03	target/ppc: Implement prefixed integer store instructions	Richard Henderson	2	-0/+16
2021-06-03	target/ppc: Move D/DS/X-form integer stores to decodetree	Richard Henderson	3	-82/+49
2021-06-03	target/ppc: Implement prefixed integer load instructions	Richard Henderson	2	-0/+31
2021-06-03	target/ppc: Move D/DS/X-form integer loads to decodetree	Richard Henderson	3	-123/+150
2021-06-03	target/ppc: Implement PNOP	Richard Henderson	2	-0/+78
2021-06-03	target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI	Richard Henderson	4	-29/+64
2021-06-03	target/ppc: Add infrastructure for prefixed insns	Richard Henderson	6	-6/+95
2021-06-03	target/ppc: Move page crossing check to ppc_tr_translate_insn	Richard Henderson	1	-3/+6
2021-06-03	target/ppc: Introduce macros to check isa extensions	Richard Henderson	1	-0/+26
2021-06-03	target/ppc: powerpc_excp: Consolidade TLB miss code	Fabiano Rosas	1	-35/+2
2021-06-03	target/ppc: powerpc_excp: Remove dump_syscall_vectored	Fabiano Rosas	1	-13/+1
2021-06-03	target/ppc: powerpc_excp: Move lpes code to where it is used	Fabiano Rosas	1	-22/+25