| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2017-09-07 | target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M | Peter Maydell | 3 | -6/+10 |
| 2017-09-07 | target/arm: Make VTOR register banked for v8M | Peter Maydell | 3 | -3/+4 |
| 2017-09-07 | target/arm: Make CONTROL register banked for v8M | Peter Maydell | 4 | -14/+17 |
| 2017-09-07 | target/arm: Make FAULTMASK register banked for v8M | Peter Maydell | 3 | -8/+31 |
| 2017-09-07 | target/arm: Make PRIMASK register banked for v8M | Peter Maydell | 3 | -5/+10 |
| 2017-09-07 | target/arm: Make BASEPRI register banked for v8M | Peter Maydell | 3 | -6/+21 |
| 2017-09-07 | target/arm: Add MMU indexes for secure v8M | Peter Maydell | 2 | -3/+25 |
| 2017-09-07 | target/arm: Register second AddressSpace for secure v8M CPUs | Peter Maydell | 1 | -7/+6 |
| 2017-09-07 | target/arm: Add state field, feature bit and migration for v8M secure state | Peter Maydell | 4 | -1/+34 |
| 2017-09-07 | target/arm: Implement new PMSAv8 behaviour | Peter Maydell | 1 | -1/+110 |
| 2017-09-07 | target/arm: Implement ARMv8M's PMSAv8 registers | Peter Maydell | 3 | -12/+66 |
| 2017-09-06 | target/arm: Perform per-insn cross-page check only for Thumb | Richard Henderson | 1 | -25/+33 |
| 2017-09-06 | target/arm: Split out thumb_tr_translate_insn | Richard Henderson | 1 | -41/+80 |
| 2017-09-06 | target/arm: Move ss check to init_disas_context | Richard Henderson | 1 | -5/+8 |
| 2017-09-06 | target/arm: [a64] Move page and ss checks to init_disas_context | Richard Henderson | 1 | -8/+9 |
| 2017-09-06 | target/arm: [tcg] Port to generic translation framework | Lluís Vilanova | 3 | -183/+41 |
| 2017-09-06 | target/arm: [tcg,a64] Port to disas_log | Lluís Vilanova | 1 | -5/+14 |
| 2017-09-06 | target/arm: [tcg] Port to disas_log | Lluís Vilanova | 1 | -5/+13 |
| 2017-09-06 | target/arm: [tcg,a64] Port to tb_stop | Lluís Vilanova | 1 | -60/+67 |
| 2017-09-06 | target/arm: [tcg] Port to tb_stop | Lluís Vilanova | 1 | -77/+84 |
| 2017-09-06 | target/arm: [tcg,a64] Port to translate_insn | Lluís Vilanova | 1 | -28/+43 |
| 2017-09-06 | target/arm: [tcg] Port to translate_insn | Lluís Vilanova | 2 | -75/+91 |
| 2017-09-06 | target/arm: [tcg,a64] Port to breakpoint_check | Lluís Vilanova | 1 | -17/+31 |
| 2017-09-06 | target/arm: [tcg,a64] Port to insn_start | Lluís Vilanova | 2 | -22/+44 |
| 2017-09-06 | target/arm: [tcg] Port to insn_start | Lluís Vilanova | 1 | -4/+11 |
| 2017-09-06 | target/arm: [tcg] Port to tb_start | Lluís Vilanova | 1 | -38/+44 |
| 2017-09-06 | target/arm: [tcg,a64] Port to init_disas_context | Lluís Vilanova | 1 | -14/+24 |
| 2017-09-06 | target/arm: [tcg] Port to init_disas_context | Lluís Vilanova | 1 | -38/+50 |
| 2017-09-06 | target/arm: [tcg] Port to DisasContextBase | Lluís Vilanova | 3 | -121/+120 |
| 2017-09-06 | target/i386: [tcg] Port to generic translation framework | Lluís Vilanova | 1 | -87/+19 |
| 2017-09-06 | target/i386: [tcg] Port to disas_log | Lluís Vilanova | 1 | -13/+19 |
| 2017-09-06 | target/i386: [tcg] Port to tb_stop | Lluís Vilanova | 1 | -12/+14 |
| 2017-09-06 | target/i386: [tcg] Port to translate_insn | Lluís Vilanova | 1 | -24/+42 |
| 2017-09-06 | target/i386: [tcg] Port to breakpoint_check | Lluís Vilanova | 1 | -12/+34 |
| 2017-09-06 | target/i386: [tcg] Port to insn_start | Lluís Vilanova | 1 | -1/+8 |
| 2017-09-06 | target/i386: [tcg] Port to init_disas_context | Lluís Vilanova | 1 | -19/+27 |
| 2017-09-06 | target/i386: [tcg] Port to DisasContextBase | Lluís Vilanova | 1 | -71/+69 |
| 2017-09-06 | target/arm: Delay check for magic kernel page | Richard Henderson | 1 | -11/+11 |
| 2017-09-06 | target: [tcg] Use a generic enum for DISAS_ values | Lluís Vilanova | 12 | -16/+64 |
| 2017-09-06 | target/arm: Use DISAS_NORETURN | Richard Henderson | 3 | -29/+30 |
| 2017-09-06 | target/i386: Use generic DISAS_* enumerators | Richard Henderson | 1 | -13/+15 |
| 2017-09-04 | target/arm: Fix aa64 ldp register writeback | Richard Henderson | 1 | -12/+17 |
| 2017-09-04 | target/arm: Allow deliver_fault() caller to specify EA bit | Peter Maydell | 2 | -5/+7 |
| 2017-09-04 | target/arm: Factor out fault delivery code | Peter Maydell | 1 | -53/+57 |
| 2017-09-04 | target/arm/kvm: pmu: improve error handling | Andrew Jones | 3 | -23/+26 |
| 2017-09-04 | hw/arm/virt: allow pmu instantiation with userspace irqchip | Andrew Jones | 2 | -3/+6 |
| 2017-09-04 | target/arm/kvm: pmu: split init and set-irq stages | Andrew Jones | 3 | -30/+40 |
| 2017-09-04 | hw/arm/virt: add pmu interrupt state | Andrew Jones | 2 | -0/+4 |
| 2017-09-04 | target/arm: Create and use new function arm_v7m_is_handler_mode() | Peter Maydell | 2 | -6/+12 |
| 2017-09-04 | target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed | Peter Maydell | 1 | -7/+8 |
