riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-05-26	target/mips: add or remove space to fix checkpatch errors	Jules Irenge	1	-81/+94
2019-05-26	mips: Decide to map PAGE_EXEC in map_address	Jakub Jermář	1	-5/+8
2019-05-26	target/mips: Refactor and fix INSERT.<B\|H\|W\|D> instructions	Mateja Marjanovic	3	-18/+71
2019-05-26	target/mips: Refactor and fix COPY_U.<B\|H\|W> instructions	Mateja Marjanovic	3	-21/+59
2019-05-26	target/mips: Refactor and fix COPY_S.<B\|H\|W\|D> instructions	Mateja Marjanovic	3	-21/+67
2019-05-26	target/mips: Fix MSA instructions ST.<B\|H\|W\|D> on big endian host	Mateja Marjanovic	1	-20/+180
2019-05-26	target/mips: Fix MSA instructions LD.<B\|H\|W\|D> on big endian host	Mateja Marjanovic	1	-20/+168
2019-05-26	target/mips: Make the results of MOD_<U\|S>.<B\|H\|W\|D> the same as on hardware	Mateja Marjanovic	1	-2/+2
2019-05-26	target/mips: Make the results of DIV_<U\|S>.<B\|H\|W\|D> the same as on hardware	Mateja Marjanovic	1	-2/+3
2019-05-24	target/riscv: Only flush TLB if SATP.ASID changes	Jonathan Behrens	1	-1/+3
2019-05-24	target/riscv: More accurate handling of `sip` CSR	Jonathan Behrens	1	-2/+5
2019-05-24	target/riscv: Add checks for several RVC reserved operands	Richard Henderson	2	-3/+14
2019-05-24	target/riscv: Add the HGATP register masks	Alistair Francis	1	-0/+11
2019-05-24	target/riscv: Add the HSTATUS register masks	Alistair Francis	1	-0/+18
2019-05-24	target/riscv: Add Hypervisor CSR macros	Alistair Francis	1	-3/+6
2019-05-24	target/riscv: Allow setting mstatus virtulisation bits	Alistair Francis	1	-9/+8
2019-05-24	target/riscv: Add the MPV and MTL mstatus bits	Alistair Francis	1	-3/+2
2019-05-24	target/riscv: Improve the scause logic	Alistair Francis	1	-1/+1
2019-05-24	target/riscv: Trigger interrupt on MIP update asynchronously	Alistair Francis	2	-8/+27
2019-05-24	target/riscv: Mark privilege level 2 as reserved	Alistair Francis	1	-1/+1
2019-05-24	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis	2	-0/+16
2019-05-24	target/riscv: Create settable CPU properties	Alistair Francis	2	-0/+57
2019-05-24	target/riscv: Remove spaces from register names	Richard Henderson	1	-8/+8
2019-05-24	target/riscv: Split gen_arith_imm into functional and temp	Richard Henderson	2	-9/+24
2019-05-24	target/riscv: Split RVC32 and RVC64 insns into separate files	Richard Henderson	6	-151/+67
2019-05-24	target/riscv: Use pattern groups in insn16.decode	Richard Henderson	3	-69/+29
2019-05-24	target/riscv: Merge argument decode for RVC shifti	Richard Henderson	3	-53/+12
2019-05-24	target/riscv: Merge argument sets for insn32 and insn16	Richard Henderson	2	-170/+58
2019-05-24	target/riscv: Use --static-decode for decodetree	Richard Henderson	2	-7/+4
2019-05-24	target/riscv: Name the argument sets for all of insn32 formats	Richard Henderson	2	-3/+25
2019-05-24	RISC-V: fix single stepping over ret and other branching instructions	Fabien Chouteau	3	-12/+32
2019-05-24	target/riscv: Do not allow sfence.vma from user mode	Jonathan Behrens	1	-3/+4
2019-05-23	arm: Remove unnecessary includes of hw/arm/arm.h	Peter Maydell	6	-6/+0
2019-05-23	target/arm: Fix vector operation segfault	Alistair Francis	1	-2/+2
2019-05-23	target/arm: Simplify BFXIL expansion	Richard Henderson	1	-3/+3
2019-05-23	target/arm: Use extract2 for EXTR	Richard Henderson	1	-16/+18
2019-05-23	Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging	Peter Maydell	10	-58/+190
2019-05-22	target/i386: Implement CPUID_EXT_RDRAND	Richard Henderson	4	-17/+73
2019-05-22	target/ppc: Use qemu_guest_getrandom for DARN	Richard Henderson	1	-11/+26
2019-05-22	target/ppc: Use gen_io_start/end around DARN	Richard Henderson	1	-6/+15
2019-05-22	target/arm: Implement ARMv8.5-RNG	Richard Henderson	3	-0/+50
2019-05-22	target/arm: Put all PAC keys into a structure	Richard Henderson	3	-24/+26
2019-05-21	target/i386: add MDS-NO feature	Paolo Bonzini	1	-1/+1
2019-05-21	target/i386: define md-clear bit	Paolo Bonzini	1	-1/+1
2019-05-21	Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190521-3' into staging	Peter Maydell	15	-5/+2499
2019-05-21	s390x/cpumodel: wire up 8561 and 8562 as gen15 machines	Christian Borntraeger	1	-4/+5
2019-05-21	s390x/cpumodel: add gen15 defintions	Christian Borntraeger	1	-0/+37
2019-05-21	s390x/cpumodel: add Deflate-conversion facility	Christian Borntraeger	5	-0/+35
2019-05-21	s390x/cpumodel: enhanced sort facility	Christian Borntraeger	5	-0/+39
2019-05-21	s390x/cpumodel: vector enhancements	Christian Borntraeger	2	-0/+4