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2019-05-22target/ppc: Use gen_io_start/end around DARNRichard Henderson1-6/+15
Generating a random number counts as I/O, as it cannot be replayed and produce the same results. Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-22target/arm: Implement ARMv8.5-RNGRichard Henderson3-0/+50
Use the newly introduced infrastructure for guest random numbers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-22target/arm: Put all PAC keys into a structureRichard Henderson3-24/+26
This allows us to use a single syscall to initialize them all. Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-21Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190521-3' into stagingPeter Maydell15-5/+2499
s390x update: - have the bios tolerate bootmap signature entries - next chunk of vector instruction support in tcg - a headers update against Linux 5.2-rc1 - add more facilities and gen15 machines to the cpu model # gpg: Signature made Tue 21 May 2019 16:09:35 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20190521-3: (55 commits) s390x/cpumodel: wire up 8561 and 8562 as gen15 machines s390x/cpumodel: add gen15 defintions s390x/cpumodel: add Deflate-conversion facility s390x/cpumodel: enhanced sort facility s390x/cpumodel: vector enhancements s390x/cpumodel: msa9 facility s390x/cpumodel: Miscellaneous-Instruction-Extensions Facility 3 s390x/cpumodel: ignore csske for expansion linux headers: update against Linux 5.2-rc1 update-linux-headers: handle new header file s390x/tcg: Implement VECTOR TEST UNDER MASK s390x/tcg: Implement VECTOR SUM ACROSS WORD s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL * s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-21s390x/cpumodel: wire up 8561 and 8562 as gen15 machinesChristian Borntraeger1-4/+5
8561 and 8562 will be gen15 machines. There is no name yet, let us use gen15a and gen15b as base name. Later on we can provide aliases with the proper name. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20190429090250.7648-10-borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21s390x/cpumodel: add gen15 defintionsChristian Borntraeger1-0/+37
add several new features (msa9, sort, deflate, additional vector instructions, new general purpose instructions) to generation 15. Also disable csske and bpb from the default and base models >=15. This will allow to migrate gen15 machines to future machines that do not have these features. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20190429090250.7648-9-borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21s390x/cpumodel: add Deflate-conversion facilityChristian Borntraeger5-0/+35
add the deflate conversion facility. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20190429090250.7648-8-borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21s390x/cpumodel: enhanced sort facilityChristian Borntraeger5-0/+39
add the enhanced sort facility. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20190429090250.7648-7-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21s390x/cpumodel: vector enhancementsChristian Borntraeger2-0/+4
Add vector enhancements to the cpu model. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20190429090250.7648-6-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21s390x/cpumodel: msa9 facilityChristian Borntraeger6-0/+114
Provide the MSA9 facility (stfle.155). This also contains pckmo subfunctions for key wrapping. Keep them in a separate group to disable those as a block if necessary. This is for example needed when disabling key wrapping via the HMC. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20190429090250.7648-5-borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21s390x/cpumodel: Miscellaneous-Instruction-Extensions Facility 3Christian Borntraeger2-0/+2
Provide the "Miscellaneous-Instruction-Extensions Facility 3" via stfle.61. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20190429090250.7648-4-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21s390x/cpumodel: ignore csske for expansionChristian Borntraeger1-0/+2
csske will be removed in a future machine. Ignore it for expanding the cpu model. Otherwise qemu falls back to z9. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Cc: qemu-stable@nongnu.org Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20190429090250.7648-3-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into stagingPeter Maydell8-1107/+2524
target/xtensa: SR reorganization and options for modern cores Reorganize special register handling to support configurations with conflicting SR definitions. Implement options used by the modern xtensa cores: - memory protection unit; - block prefetch; - exclusive access Add special register definitions and IRQ types for ECC/parity, gather/scatter and IDMA. # gpg: Signature made Mon 20 May 2019 18:53:05 BST # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20190520-xtensa: target/xtensa: implement exclusive access option target/xtensa: update list of exception causes target/xtensa: implement block prefetch option opcodes target/xtensa: implement DIWBUI.P opcode target/xtensa: implement MPU option target/xtensa: add parity/ECC option SRs target/xtensa: define IDMA and gather/scatter IRQ types target/xtensa: make internal MMU functions static target/xtensa: get rid of centralized SR properties Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-19target/alpha: Fix user-only floating-point exceptionsRichard Henderson3-5/+78
Record the software fp control register, as set by the osf_setsysinfo syscall. Add those masked exceptions to fpcr_exc_enable. Do not raise a signal for masked fp exceptions. Fixes: https://bugs.launchpad.net/bugs/1701835 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-19target/alpha: Clean up alpha_cpu_dump_stateRichard Henderson1-9/+10
Drop the "RI" and "FIR" prefixes; use only the normal linux names. Add the FPCR to the dump. Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-17Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2-1/+2
Mostly bugfixes and cleanups, the most important being "megasas: fix mapped frame size" from Peter Lieven. In addition, -realtime is marked as deprecated. # gpg: Signature made Fri 17 May 2019 14:25:11 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (21 commits) hw/net/ne2000: Extract the PCI device from the chipset common code hw/char: Move multi-serial devices into separate file ioapic: allow buggy guests mishandling level-triggered interrupts to make progress build: don't build hardware objects with linux-user build: chardev is only needed for softmmu targets configure: qemu-ga is only needed with softmmu targets build: replace GENERATED_FILES by generated-files-y trace: only include trace-event-subdirs when they are needed sun4m: obey -vga none mips-fulong2e: obey -vga none hw/i386/acpi: Assert a pointer is not null BEFORE using it hw/i386/acpi: Add object_resolve_type_unambiguous to improve modularity hw/acpi/piix4: Move TYPE_PIIX4_PM to a public header memory: correct the comment to DIRTY_MEMORY_MIGRATION vl: fix -sandbox parsing crash when seccomp support is disabled hvf: Add missing break statement megasas: fix mapped frame size vl: Add missing descriptions to the VGA adapters list Declare -realtime as deprecated roms: assert if max rom size is less than the used size ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-17build: replace GENERATED_FILES by generated-files-yLaurent Vivier1-1/+1
When possible use generated-files-$(FLAG) to disable some targets (like KEYCODEMAP_FILES). Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20190401141222.30034-3-lvivier@redhat.com>
2019-05-17Merge remote-tracking branch 'remotes/vivier/tags/m68k-staging-pull-request' ↵Peter Maydell5-38/+84
into staging code cleanup, switch to transaction_failed hook # gpg: Signature made Thu 16 May 2019 23:33:00 BST # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-staging-pull-request: target/m68k: Optimize rotate_x() using extract_i32() target/m68k: Fix a tcg_temp leak target/m68k: Reduce the l1 TCGLabel scope target/m68k: Switch to transaction_failed hook target/m68k: In get_physical_address() check for memory access failures target/m68k: In dump_address_map() check for memory access failures Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/m68k/cpu.h
2019-05-17s390x/tcg: Implement VECTOR TEST UNDER MASKDavid Hildenbrand4-0/+45
Let's return the cc value directly via cpu_env. Unfortunately there isn't a simple way to calculate the value lazily - one would have to calculate and store e.g. the population count of the mask and the result so it can be evaluated in a cc helper. But as VTM only sets the cc, we can assume the value will be needed soon either way. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUM ACROSS WORDDavid Hildenbrand2-0/+31
Similar to VECTOR SUM ACROSS DOUBLEWORD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUM ACROSS QUADWORDDavid Hildenbrand2-0/+34
Similar to VECTOR SUM ACROSS DOUBLEWORD, however without a loop and using 128-bit calculations. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORDDavid Hildenbrand2-0/+31
Perform the calculations without a helper. Only 16 bit or 32 bit values have to be added. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATIONDavid Hildenbrand2-0/+36
Mostly courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATIONDavid Hildenbrand2-0/+28
Fairly easy as only 128-bit handling is required. Simply perform the subtraction and then subtract the borrow. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATIONDavid Hildenbrand4-0/+72
Let's keep it simple for now and handle 8/16 bit elements via helpers. Especially for 8/16, we could come up with some bit tricks. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUBTRACTDavid Hildenbrand2-0/+19
We can use tcg_gen_sub2_i64() to do 128-bit subtraction and otherwise existing gvec helpers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL *David Hildenbrand4-0/+28
Similar to VECTOR SHIFT RIGHT ARITHMETICAL. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETICDavid Hildenbrand4-0/+48
Similar to VECTOR SHIFT LEFT ARITHMETIC. Add s390_vec_sar() similar to s390_vec_shr(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTEDavid Hildenbrand2-0/+31
Inline expansion courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE)David Hildenbrand4-0/+31
We can reuse the existing 128-bit shift utility function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ELEMENT SHIFTDavid Hildenbrand2-0/+93
We can use all the fancy new vector helpers implemented by Richard. One important thing to take care of is always to properly mask of unused bits from the shift count. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASKDavid Hildenbrand4-0/+75
Use the new vector expansion for GVecGen3i. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICALDavid Hildenbrand4-0/+98
Take care of properly taking the modulo of the count. We might later want to come back and create a variant of VERLL where the base register is 0, resulting in an immediate. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR POPULATION COUNTDavid Hildenbrand4-0/+37
Similar to VECTOR COUNT TRAILING ZEROES. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR OR WITH COMPLEMENTDavid Hildenbrand2-0/+9
Again, vector enhancements facility 1 material. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ORDavid Hildenbrand2-0/+9
Reuse a gvec helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR NOT EXCLUSIVE ORDavid Hildenbrand2-0/+9
Again, part of vector enhancement facility 1. The operation corresponds to an bitwise equality check. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR NORDavid Hildenbrand2-0/+9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR NANDDavid Hildenbrand3-0/+10
Part of vector enhancements facility 1, but easy to implement. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR MULTIPLY *David Hildenbrand4-0/+218
Yet another set of variants. Implement it similar to VECTOR MULTIPLY AND ADD *. At least for one variant we have a gvec helper we can reuse. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR MULTIPLY AND ADD *David Hildenbrand4-0/+277
Quite some variants to handle. At least handle some 32-bit element variants via gvec expansion (we could also handle 16/32-bit variants for ODD and EVEN easily via gvec expansion, but let's keep it simple for now). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR (MAXIMUM|MINIMUM) (LOGICAL)David Hildenbrand2-0/+39
Luckily, we already have gvec helpers for all four cases. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR LOAD POSITIVEDavid Hildenbrand2-0/+15
Similar to VECTOR LOAD COMPLEMENT. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR LOAD COMPLEMENTDavid Hildenbrand2-0/+18
We can reuse an existing gvec helper for negating the values. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR GALOIS FIELD MULTIPLY SUM (AND ACCUMULATE)David Hildenbrand4-0/+217
A galois field multiplication in field 2 is like binary multiplication, however instead of doing ordinary binary additions, xor's are performed. So no carries are considered. Implement all variants via helpers. s390_vec_sar() and s390_vec_shr() will be reused later on. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR EXCLUSIVE ORDavid Hildenbrand2-0/+9
Easy, we can reuse an existing gvec helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR COUNT TRAILING ZEROSDavid Hildenbrand4-0/+46
Implement it similar to VECTOR COUNT LEADING ZEROS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR COUNT LEADING ZEROSDavid Hildenbrand4-0/+49
For 8/16, use the 32 bit variant and properly subtract the added leading zero bits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR COMPARE *David Hildenbrand6-0/+54
To carry out the comparison, we can reuse the existing gvec comparison function. In case the CC is to be computed, save the result vector and compute the CC lazily. The result is a vector consisting of all 1's for elements that matched and 0's for elements that didn't match. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ELEMENT COMPARE *David Hildenbrand2-0/+24
Fairly easy to implement, we can make use of the existing CC helpers cmps64 and cmpu64 - we siply have to sign extend the elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
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