riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-09-07	target/riscv: Update the privilege field for sscofpmf CSRs	Atish Patra	1	-30/+60
2022-09-07	hw/riscv: virt: Add PMU DT node to the device tree	Atish Patra	2	-0/+58
2022-09-07	target/riscv: Add few cache related PMU events	Atish Patra	1	-0/+25
2022-09-07	target/riscv: Simplify counter predicate function	Atish Patra	1	-101/+9
2022-09-07	target/riscv: Add sscofpmf extension support	Atish Patra	7	-11/+623
2022-09-07	target/riscv: Add vstimecmp support	Atish Patra	6	-6/+118
2022-09-07	target/riscv: Add stimecmp support	Atish Patra	8	-1/+235
2022-09-07	hw/intc: Move mtimer/mtimecmp to aclint	Atish Patra	2	-5/+2
2022-09-07	target/riscv: Use official extension names for AIA CSRs	Anup Patel	4	-14/+26
2022-09-07	target/riscv: Add xicondops in ISA entry	Rahul Pathak	1	-0/+1
2022-09-07	target/riscv: Remove additional priv version check for mcountinhibit	Atish Patra	1	-8/+0
2022-09-07	target/riscv: Fix priority of csr related check in riscv_csrrw_check	Weiwei Li	1	-19/+25
2022-09-07	target/riscv: Add Zihintpause support	Dao Lu	4	-1/+25
2022-09-07	target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti...	eopXD	1	-0/+1
2022-09-07	target/riscv: rvv: Add mask agnostic for vector permutation instructions	Yueh-Ting (eop) Chen	2	-2/+25
2022-09-07	target/riscv: rvv: Add mask agnostic for vector mask instructions	Yueh-Ting (eop) Chen	2	-0/+14
2022-09-07	target/riscv: rvv: Add mask agnostic for vector floating-point instructions	Yueh-Ting (eop) Chen	2	-0/+38
2022-09-07	target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct...	Yueh-Ting (eop) Chen	1	-10/+16
2022-09-07	target/riscv: rvv: Add mask agnostic for vector integer comparison instructions	Yueh-Ting (eop) Chen	2	-0/+11
2022-09-07	target/riscv: rvv: Add mask agnostic for vector integer shift instructions	Yueh-Ting (eop) Chen	2	-0/+8
2022-09-07	target/riscv: rvv: Add mask agnostic for vx instructions	Yueh-Ting (eop) Chen	2	-0/+5
2022-09-07	target/riscv: rvv: Add mask agnostic for vector load / store instructions	Yueh-Ting (eop) Chen	2	-11/+29
2022-09-07	target/riscv: rvv: Add mask agnostic for vv instructions	Yueh-Ting (eop) Chen	6	-2/+20
2022-09-07	target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V	Alexey Baturo	1	-1/+1
2022-09-07	target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c...	Weiwei Li	1	-13/+5
2022-09-07	target/riscv: Fix checks in hmode/hmode32	Weiwei Li	2	-7/+7
2022-09-07	target/riscv: Add check for csrs existed with U extension	Weiwei Li	1	-3/+21
2022-09-07	target/riscv: Fix checkpatch warning may triggered in csr_ops table	Weiwei Li	1	-207/+234
2022-09-07	target/riscv: H extension depends on I extension	Weiwei Li	1	-0/+6
2022-09-07	target/riscv: Add check for supported privilege mode combinations	Weiwei Li	1	-0/+6
2022-09-07	target/riscv: move zmmul out of the experimental properties	Weiwei Li	1	-1/+2
2022-09-07	target/riscv: fix shifts shamt value for rv128c	Frédéric Pétrot	2	-5/+22
2022-09-07	target/riscv: Force disable extensions if priv spec version does not match	Anup Patel	1	-56/+94
2022-09-07	target/riscv: Update [m\|h]tinst CSR in riscv_cpu_do_interrupt()	Anup Patel	3	-6/+296
2022-09-06	target/riscv: Make translator stop before the end of a page	Richard Henderson	1	-4/+13
2022-09-06	target/riscv: Add MAX_INSN_LEN and insn_len	Richard Henderson	1	-1/+9
2022-09-06	target/i386: Make translator stop before the end of a page	Ilya Leoshkevich	1	-24/+38
2022-09-06	target/s390x: Make translator stop before the end of a page	Ilya Leoshkevich	1	-4/+11
2022-09-06	accel/tcg: Add pc and host_pc params to gen_intermediate_code	Richard Henderson	21	-42/+68
2022-09-06	accel/tcg: Remove translator_ldsw	Richard Henderson	1	-1/+1
2022-09-04	target/openrisc: Interrupt handling fixes	Stafford Horne	2	-1/+7
2022-09-04	target/openrisc: Enable MTTCG	Stafford Horne	2	-1/+8
2022-09-04	target/openrisc: Add interrupted CPU to log	Stafford Horne	1	-1/+3
2022-09-04	target/openrisc: Fix memory reading in debugger	Stafford Horne	1	-1/+7
2022-09-02	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Stefan Hajnoczi	5	-1329/+1465
2022-09-01	Merge tag 'pull-avr-20220901' of https://gitlab.com/rth7680/qemu into staging	Stefan Hajnoczi	2	-30/+65
2022-09-01	target/i386: AVX+AES helpers prep	Paul Brook	1	-19/+22
2022-09-01	target/i386: AVX pclmulqdq prep	Paul Brook	1	-7/+22
2022-09-01	target/i386: Rewrite blendv helpers	Paul Brook	1	-62/+24
2022-09-01	target/i386: Misc AVX helper prep	Paul Brook	1	-49/+94