riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-06-02	target/m68k: Fix pc, c flag, and address argument for EXCP_DIV0	Richard Henderson	3	-42/+51
2022-06-02	target/m68k: Fix address argument for EXCP_CHK	Richard Henderson	2	-25/+35
2022-06-02	target/m68k: Remove retaddr in m68k_interrupt_all	Richard Henderson	1	-9/+6
2022-06-02	target/m68k: Fix coding style in m68k_interrupt_all	Richard Henderson	1	-2/+2
2022-06-02	target/m68k: Switch over exception type in m68k_interrupt_all	Richard Henderson	1	-19/+30
2022-06-02	target/m68k: Raise the TRAPn exception with the correct pc	Richard Henderson	2	-10/+1
2022-05-26	target/m68k: Enable halt insn for 68060	Richard Henderson	1	-0/+1
2022-05-26	target/m68k: Clear mach in m68k_cpu_disas_set_info	Richard Henderson	1	-5/+1
2022-05-25	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Richard Henderson	4	-24/+82
2022-05-25	i386: Hyper-V Direct TLB flush hypercall	Vitaly Kuznetsov	4	-0/+12
2022-05-25	i386: Hyper-V Support extended GVA ranges for TLB flush hypercalls	Vitaly Kuznetsov	4	-0/+12
2022-05-25	i386: Hyper-V XMM fast hypercall input feature	Vitaly Kuznetsov	4	-1/+11
2022-05-25	i386: Hyper-V Enlightened MSR bitmap feature	Vitaly Kuznetsov	4	-0/+15
2022-05-25	i386: Use hv_build_cpuid_leaf() for HV_CPUID_NESTED_FEATURES	Vitaly Kuznetsov	2	-11/+15
2022-05-25	target/i386/kvm: Fix disabling MPX on "-cpu host" with MPX-capable host	Maciej S. Szmigiero	1	-0/+8
2022-05-24	target/riscv: add zicsr/zifencei to isa_string	Hongren (Zenithal) Zheng	1	-0/+2
2022-05-24	target/riscv: Set [m\|s]tval for both illegal and virtual instruction traps	Anup Patel	4	-5/+23
2022-05-24	target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode	Anup Patel	1	-2/+1
2022-05-24	target/riscv: Fix csr number based privilege checking	Anup Patel	1	-2/+6
2022-05-24	target/riscv: Fix typo of mimpid cpu option	Frank Chang	3	-7/+7
2022-05-24	target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize	Weiwei Li	1	-12/+12
2022-05-24	target/riscv: Move/refactor ISA extension checks	Tsukasa OI	1	-15/+16
2022-05-24	target/riscv: FP extension requirements	Tsukasa OI	1	-0/+25
2022-05-24	target/riscv: Change "G" expansion	Tsukasa OI	1	-2/+5
2022-05-24	target/riscv: Disable "G" by default	Tsukasa OI	1	-1/+1
2022-05-24	target/riscv: Fix coding style on "G" expansion	Tsukasa OI	1	-2/+2
2022-05-24	target/riscv: Add short-isa-string option	Tsukasa OI	2	-1/+7
2022-05-24	target/riscv: Move Zhinx* extensions on ISA string	Tsukasa OI	1	-2/+2
2022-05-24	target/riscv: rvv: Fix early exit condition for whole register load/store	eopXD	1	-27/+31
2022-05-24	target/riscv: Fix VS mode hypervisor CSR access	Dylan Reid	1	-5/+5
2022-05-23	target/i386: Remove LBREn bit check when access Arch LBR MSRs	Yang Weijiang	1	-12/+9
2022-05-19	target/arm: Use FIELD definitions for CPACR, CPTR_ELx	Richard Henderson	3	-35/+74
2022-05-19	target/arm: Enable FEAT_HCX for -cpu max	Richard Henderson	3	-0/+71
2022-05-19	target/arm: Fix PAuth keys access checks for disabled SEL2	Florian Lugou	1	-1/+1
2022-05-19	target/arm: Make number of counters in PMCR follow the CPU	Peter Maydell	6	-12/+47
2022-05-19	target/arm/helper.c: Delete stray obsolete comment	Peter Maydell	1	-1/+0
2022-05-19	Fix aarch64 debug register names.	Chris Howard	1	-4/+12
2022-05-19	hw/intc/arm_gicv3: Use correct number of priority bits for the CPU	Peter Maydell	2	-0/+7
2022-05-19	target/arm: Drop unsupported_encoding() macro	Peter Maydell	2	-13/+4
2022-05-19	target/arm: Implement FEAT_IDST	Peter Maydell	5	-2/+65
2022-05-19	target/arm: Enable FEAT_S2FWB for -cpu max	Peter Maydell	1	-0/+11
2022-05-19	target/arm: Implement FEAT_S2FWB	Peter Maydell	2	-3/+86
2022-05-19	target/arm: Factor out FWB=0 specific part of combine_cacheattrs()	Peter Maydell	1	-38/+50
2022-05-19	target/arm: Postpone interpretation of stage 2 descriptor attribute bits	Peter Maydell	2	-7/+42
2022-05-16	Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu in...	Richard Henderson	1	-1/+1
2022-05-16	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Richard Henderson	5	-188/+364
2022-05-16	target/i386: Fix sanity check on max APIC ID / X2APIC enablement	David Woodhouse	1	-1/+1
2022-05-15	Merge tag 'or1k-pull-request-20220515' of https://github.com/stffrdhrn/qemu i...	Richard Henderson	1	-0/+11
2022-05-15	target/openrisc: Do not reset delay slot flag on early tb exit	Stafford Horne	1	-0/+11
2022-05-14	target/i386: Support Arch LBR in CPUID enumeration	Yang Weijiang	1	-1/+19