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2019-02-18target/ppc: convert vaddu[b,h,w,d] and vsubu[b,h,w,d] over to use vector ↵Mark Cave-Ayland3-23/+8
operations Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190215100058.20015-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-18target/ppc: convert VMX logical instructions to use vector operationsMark Cave-Ayland2-31/+17
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190215100058.20015-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17target/ppc: Disable ISA 2.06 PM instructions on POWER9Benjamin Herrenschmidt1-1/+1
The ISA 2.06/2.07 Power Management instructions (doze, nap & rvwinkle) don't exist on POWER9, don't enable them. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190128094625.4428-13-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17ppc: fix crash during branch steppingRoman Kapl1-22/+15
The PPC BRANCH exception could bubble up, but this is an QEMU internal exception and QEMU then crased. Instead it should trigger TRACE exception, according to PPC 2.07 book. It could happen only when using branch stepping, which is not commonly used. Change gen_prep_dbgex do do trigger TRACE. The excp, argument is now removed, since the type of exception can be inferred from the singlestep_enabled flags. removed the guards around gen_exception, since they are unnecessary. Fixes: 0e3bf48909 ("ppc: add DBCR based debugging"). Signed-off-by: Roman Kapl <rka@sysgo.com> Message-Id: <20190212121255.2279-1-rka@sysgo.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17target/ppc: Remove some #if 0'ed codeBenjamin Herrenschmidt2-24/+0
Some debug stuff we don't need to keep there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190128094625.4428-7-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17target/ppc: Fix msync to do what hardware doesBALATON Zoltan1-3/+8
According to BookE docs, invalid bits (while undefined behaviour) should not raise exception but be ignored. This seems to be implementation dependent though and QEMU currently does what e500 CPUs do and raise exception for invalid bits. Unfortunately some versions of libstdc++ (and so all programs compiled with it) have lwsync on PPC440 which is invalid but on real hardware it's just executed as msync ignoring the invalid bits (maybe that's why it got undetected) but they fail on QEMU. This patch changes invalid mask of msync to allow these programs to run but keep generating exception on e500 cores to follow what hardware does. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17target/ppc: Enable reporting of SPRs to GDBFabiano Rosas4-2/+130
This allows reading and writing of SPRs via GDB: (gdb) p/x $srr1 $1 = 0x8000000002803033 (gdb) p/x $pvr $2 = 0x4b0201 (gdb) set $pvr=0x4b0000 (gdb) p/x $pvr $3 = 0x4b0000 The `info` command can also be used: (gdb) info registers spr For this purpose, GDB needs to be provided with an XML description of the registers (see the gdb-xml directory for examples) and a set of callbacks for reading and writing the registers must be defined. The XML file in this case is created dynamically, based on the SPRs already defined in the machine. This way we avoid the need for several XML files to suit each possible ppc machine. The gdb_{get,set}_spr_reg callbacks take an index based on the order the registers appear in the XML file. This index does not match the actual location of the registers in the env->spr array so the gdb_find_spr_idx function does that conversion. Note: GDB currently needs to know the guest endianness in order to properly print the registers values. This is done automatically by GDB when provided with the ELF file or explicitly with the `set endian <big|little>` command. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-15target/arm: Add missing clear_tail callsRichard Henderson1-0/+2
Fortunately, the functions affected are so far only called from SVE, so there is no tail to be cleared. But as we convert more of AdvSIMD to gvec, this will matter. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-13-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Use vector operations for saturationRichard Henderson5-44/+331
For same-sign saturation, we have tcg vector operations. We can compute the QC bit by comparing the saturated value against the unsaturated value. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-12-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Split out FPSCR.QC to a vector fieldRichard Henderson4-7/+21
Change the representation of this field such that it is easy to set from vector code. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-11-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]Richard Henderson1-7/+8
Given that we mask bits properly on set, there is no reason to mask them again on get. We failed to clear the exception status bits, 0x9f, which means that the wrong value would be returned on get. Except in the (probably normal) case in which the set clears all of the bits. Simplify the code in set to also clear the RES0 bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Split out flags setting from vfp comparesRichard Henderson1-18/+27
Minimize the code within a macro by splitting out a helper function. Use deposit32 instead of manual bit manipulation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Fix arm_cpu_dump_state vs FPSCRRichard Henderson1-1/+1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Fix vfp_gdb_get/set_reg vs FPSCRRichard Henderson1-2/+2
The components of this register is stored in several different locations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-7-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Remove neon min/max helpersRichard Henderson2-24/+0
These are now unused. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Use tcg integer min/max primitives for neonRichard Henderson1-4/+4
The 32-bit PMIN/PMAX has been decomposed to scalars, and so can be trivially expanded inline. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Use vector minmax expanders for aarch32Richard Henderson1-6/+19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Use vector minmax expanders for aarch64Richard Henderson1-21/+14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Rely on optimization within tcg_gen_gvec_orRichard Henderson3-19/+5
Since we're now handling a == b generically, we no longer need to do it by hand within target/arm/. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15arm: Allow system registers for KVM guests to be changed by QEMU codePeter Maydell5-22/+38
At the moment the Arm implementations of kvm_arch_{get,put}_registers() don't support having QEMU change the values of system registers (aka coprocessor registers for AArch32). This is because although kvm_arch_get_registers() calls write_list_to_cpustate() to update the CPU state struct fields (so QEMU code can read the values in the usual way), kvm_arch_put_registers() does not call write_cpustate_to_list(), meaning that any changes to the CPU state struct fields will not be passed back to KVM. The rationale for this design is documented in a comment in the AArch32 kvm_arch_put_registers() -- writing the values in the cpregs list into the CPU state struct is "lossy" because the write of a register might not succeed, and so if we blindly copy the CPU state values back again we will incorrectly change register values for the guest. The assumption was that no QEMU code would need to write to the registers. However, when we implemented debug support for KVM guests, we broke that assumption: the code to handle "set the guest up to take a breakpoint exception" does so by updating various guest registers including ESR_EL1. Support this by making kvm_arch_put_registers() synchronize CPU state back into the list. We sync only those registers where the initial write succeeds, which should be sufficient. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Dongjiu Geng <gengdongjiu@huawei.com>
2019-02-15target/arm: expose remaining CPUID registers as RAZAlex Bennée2-3/+26
There are a whole bunch more registers in the CPUID space which are currently not used but are exposed as RAZ. To avoid too much duplication we expand ARMCPRegUserSpaceInfo to understand glob patterns so we only need one entry to tweak whole ranges of registers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190205190224.2198-5-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: expose MPIDR_EL1 to userspaceAlex Bennée1-7/+14
As this is a single register we could expose it with a simple ifdef but we use the existing modify_arm_cp_regs mechanism for consistency. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190205190224.2198-4-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: expose CPUID registers to userspaceAlex Bennée2-0/+80
A number of CPUID registers are exposed to userspace by modern Linux kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's user-mode emulation we don't need to emulate the kernels trap but just return the value the trap would have done. To avoid too much #ifdef hackery we process ARMCPRegInfo with a new helper (modify_arm_cp_regs) before defining the registers. The modify routine is driven by a simple data structure which describes which bits are exported and which are fixed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190205190224.2198-3-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: relax permission checks for HWCAP_CPUID registersAlex Bennée2-1/+17
Although technically not visible to userspace the kernel does make them visible via a trap and emulate ABI. We provide a new permission mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust the minimum permission check accordingly. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190205190224.2198-2-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_beCatherine Ho1-2/+2
The lo,hi order is different from the comments. And in commit 1ec182c33379 ("target/arm: Convert to HAVE_CMPXCHG128"), it changes the original code logic. So just restore the old code logic before this commit: do_paired_cmpxchg64_be(): cmpv = int128_make128(env->exclusive_high, env->exclusive_val); newv = int128_make128(new_hi, new_lo); This fixes a bug that would only be visible for big-endian AArch64 guest code. Fixes: 1ec182c33379 ("target/arm: Convert to HAVE_CMPXCHG128") Signed-off-by: Catherine Ho <catherine.hecx@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1548985244-24523-1-git-send-email-catherine.hecx@gmail.com [PMM: added note that bug only affects BE guests] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15target/arm: Implement HACR_EL2Peter Maydell1-0/+6
HACR_EL2 is a register with IMPDEF behaviour, which allows implementation specific trapping to EL2. Implement it as RAZ/WI, since QEMU's implementation has no extra traps. This also matches what h/w implementations like Cortex-A53 and A57 do. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190205181218.8995-1-peter.maydell@linaro.org
2019-02-15target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTRAaron Lindsay OS1-4/+4
This bug was introduced in: commit 5ecdd3e47cadae83a62dc92b472f1fe163b56f59 target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190205135129.19338-1-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-14target/mips: introduce MTTCG-enabled buildsAleksandar Markovic1-0/+2
Introduce MTTCG-enabled QEMU builds for mips32, mipsn32, and mips64. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2019-02-14target/mips: hold BQL in mips_vpe_wake()Goran Ferenc1-0/+3
Hold BQL whenever mips_vpe_wake() is invoked. Without this patch, MIPS MT with MTTCG enabled triggers an abort in tcg_handle_interrupt() due to an unlocked access to cpu_interrupt(). This patch makes sure that the BQL is held in this case. Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2019-02-14hw/mips_int: hold BQL for all interrupt requestsAleksandar Markovic1-18/+3
Make sure BQL is held for all interrupt requests. For MTTCG-enabled configurations, handling soft and hard interrupts between vCPUs must be properly locked. By acquiring BQL, make sure all paths triggering an IRQ are synchronized. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2019-02-14target/mips: reimplement SC instruction emulation and use cmpxchgLeon Alrae5-118/+44
Completely rewrite conditional stores handling. Use cmpxchg. This eliminates need for separate implementations of SC instruction emulation for user and system emulation. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-14target/mips: compare virtual addresses in LL/SC sequenceLeon Alrae4-18/+25
Do only virtual addresses comaprisons in LL/SC sequence emulations. Until this patch, physical addresses had been compared in SC part of LL/SC sequence, even though such comparisons could be avoided. Getting rid of them allows throwing away SC helpers and having common SC implementations in user and system mode, avoiding the need for two separate implementations selected by #ifdef CONFIG_USER_ONLY. Correct guest software should not rely on LL/SC if they accesses the same physical address via different virtual addresses or if page mapping gets changed between LL/SC due to manipulating TLB entries. MIPS Instruction Set Manual clearly says that an RMW sequence must use the same address in the LL and SC (virtual address, physical address, cacheability and coherency attributes must be identical). Otherwise, the result of the SC is not predictable. This patch takes advantage of this fact and removes the virtual->physical address translation from SC helper. lladdr served as Coprocessor 0 LLAddr register which captures physical address of the most recent LL instruction, and also lladdr was used for comparison with following SC physical address. This patch changes the meaning of lladdr - now it will only keep the virtual address of the most recent LL. Additionally, CP0_LLAddr field is introduced which is the actual Coperocessor 0 LLAddr register that guest can access. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf1' ↵Peter Maydell8-106/+394
into staging RISC-V Patches for the 4.0 Soft Freeze, Part 1 This patch set contains a handful of patches I've collected over the last few weeks. There's nothing really fundamental, but I thought it would be good to send these out now as there are some other patch sets on the mailing list that are getting ready to go. As far as the actual patches, there's: * A set that cleans up our FS dirty-mode handling. * Support for writing MISA. * The removal of Michael as a maintainer. * A fix to {m,s}counteren handling. * A fix to make sure the kernel's start address is computed correctly on 32-bit targets. This makes my "RISC-V Patches for 3.2, Part 3" pull request defunct, as it contains the same patches but based on a newer master. As usual, I've tested this using a Fedora boot on the latest Linux. This patch set does not include Bastian's decodetree patches because there were some merge conflicts and while I've cleaned them up I want to get a round of review first. # gpg: Signature made Wed 13 Feb 2019 15:37:50 GMT # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.0-sf1: riscv: Ensure the kernel start address is correctly cast target/riscv: fix counter-enable checks in ctr() MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer RISC-V: Add misa runtime write support RISC-V: Add misa.MAFD checks to translate RISC-V: Add misa to DisasContext RISC-V: Add priv_ver to DisasContext RISC-V: Use riscv prefix consistently on cpu helpers RISC-V: Implement mstatus.TSR/TW/TVM RISC-V: Mark mstatus.fs dirty RISC-V: Split out mstatus_fs from tb_flags Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-12target/hppa: fix dcor instructionSven Schnelle1-1/+1
It looks like the operands where exchanged. HP bootrom tests the following sequence: 0x00000000f0004064: ldil L%-66666800,r7 0x00000000f0004068: addi 19f,r7,r7 0x00000000f000406c: addi -1,r0,rp 0x00000000f0004070: addi f,r0,r4 0x00000000f0004074: addi 1,r4,r5 0x00000000f0004078: dcor rp,r6 0x00000000f000407c: cmpb,<>,n r6,r7,0xf000411 This returned 0x66666661 instead of the expected 0x9999999f in QEMU. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190211181907.2219-6-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Fix addition '</<=' conditionsSven Schnelle1-36/+57
These conditions include the signed overflow bit. See page 5-3 of the Parisc 1.1 Architecture Reference Manual for details. Signed-off-by: Sven Schnelle <svens@stackframe.org> [rth: More changes for c == 3, to compute (N^V)|Z properly.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Rearrange log conditionsRichard Henderson1-7/+49
We will be fixing do_cond vs signed overflow, which requires that do_log_cond not rely on do_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: move GETPC to HELPER() functionsSven Schnelle1-10/+6
When QEMU is compiled with -O0, these functions are inlined which will cause a wrong restart address generated for the TB. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190211181907.2219-2-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Merge translate_one into hppa_tr_translate_insnRichard Henderson1-8/+3
Now that the implementation is entirely within the generated decode function, eliminate the wrapper. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Convert fp operate insnsRichard Henderson2-435/+483
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Convert fp fused multiply-add insnsRichard Henderson2-53/+36
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Convert halt/reset insnsRichard Henderson2-33/+19
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Convert fp indexed memory insnsRichard Henderson2-93/+21
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Convert offset memory insnsRichard Henderson2-165/+99
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Convert arithmetic immediate insnsRichard Henderson2-89/+92
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Convert direct and indirect branchesRichard Henderson2-102/+63
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Convert shift, extract, deposit insnsRichard Henderson2-136/+94
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Convert conditional branchesRichard Henderson2-126/+123
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Convert fp multiply-addRichard Henderson2-29/+52
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Convert indexed memory insnsRichard Henderson2-133/+60
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12target/hppa: Convert arithmetic/logical insnsRichard Henderson2-167/+189
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-01-04 03:28:05 +0000