riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-01-11	target/i386: fix operand size of unary SSE operations	Paolo Bonzini	1	-5/+6
2023-01-11	target/i386: Remove compilation errors when -Werror=maybe-uninitialized	Eric Auger	1	-0/+4
2023-01-11	i386: Emit correct error code for 64-bit IDT entry	Joe Richey	1	-4/+4
2023-01-09	Merge tag 'pull-request-2023-01-09' of https://gitlab.com/thuth/qemu into sta...	Peter Maydell	5	-7/+14
2023-01-09	target/s390x: Restrict sysemu/reset.h to system emulation	Philippe Mathieu-Daudé	1	-1/+3
2023-01-09	target/s390x/tcg/excp_helper: Restrict system headers to sysemu	Philippe Mathieu-Daudé	1	-4/+4
2023-01-09	target/s390x/tcg/misc_helper: Remove unused "memory.h" include	Philippe Mathieu-Daudé	1	-1/+0
2023-01-09	hw/s390x/pv: Restrict Protected Virtualization to sysemu	Philippe Mathieu-Daudé	2	-1/+7
2023-01-08	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Peter Maydell	2	-6/+13
2023-01-06	Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qem...	Peter Maydell	18	-108/+874
2023-01-06	Merge tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu into staging	Peter Maydell	4	-46/+10
2023-01-06	Merge tag 'pull-hex-20230105' of https://github.com/quic/qemu into staging	Peter Maydell	6	-15/+56
2023-01-06	RISC-V: Add Zawrs ISA extension support	Christoph Muellner	5	-0/+64
2023-01-06	target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+	Bin Meng	1	-0/+6
2023-01-06	target/riscv: Simplify helper_sret() a little bit	Bin Meng	1	-14/+6
2023-01-06	target/riscv: Set pc_succ_insn for !rvc illegal insn	Richard Henderson	1	-8/+4
2023-01-06	target/riscv: Fix mret exception cause when no pmp rule is configured	Bin Meng	1	-1/+1
2023-01-06	target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()	Bin Meng	1	-0/+4
2023-01-06	target/riscv: support cache-related PMU events in virtual mode	Jim Shu	1	-1/+1
2023-01-06	target/riscv: Typo fix in sstc() predicate	Anup Patel	1	-1/+1
2023-01-06	target/riscv: Add itrigger_enabled field to CPURISCVState	LIU Zhiwei	4	-2/+20
2023-01-06	target/riscv: Enable native debug itrigger	LIU Zhiwei	1	-0/+72
2023-01-06	target/riscv: Add itrigger support when icount is enabled	LIU Zhiwei	4	-0/+65
2023-01-06	target/riscv: Add itrigger support when icount is not enabled	LIU Zhiwei	9	-11/+131
2023-01-06	target/riscv: generate virtual instruction exception	Mayuresh Chitale	1	-1/+7
2023-01-06	target/riscv: smstateen check for h/s/envcfg	Mayuresh Chitale	1	-7/+80
2023-01-06	target/riscv: Add smstateen support	Mayuresh Chitale	4	-0/+378
2023-01-06	target/riscv: Fix PMP propagation for tlb	LIU Zhiwei	3	-70/+42
2023-01-06	target/i386: Add SGX aex-notify and EDECCSSA support	Kai Huang	1	-2/+2
2023-01-06	KVM: remove support for kernel-irqchip=off	Paolo Bonzini	1	-4/+11
2023-01-05	target/sparc: Avoid TCGV_{LOW,HIGH}	Richard Henderson	1	-17/+4
2023-01-05	Hexagon (target/hexagon) implement mutability mask for GPRs	Marco Liebel	1	-2/+42
2023-01-05	target/hexagon: suppress unused variable warning	Alessandro Di Federico	2	-1/+2
2023-01-05	target/hexagon/idef-parser: fix two typos in README	Matheus Tavares Bernardino	1	-2/+2
2023-01-05	target/hexagon: rename aliased register HEX_REG_P3_0	Mukilan Thiyagarajan	3	-10/+10
2023-01-05	target/arm: align exposed ID registers with Linux	Zhuojia Shen	1	-17/+79
2023-01-05	target/arm: cleanup cpu includes	Claudio Fontana	2	-7/+0
2023-01-05	target/arm: Remove unused includes from helper.c	Fabiano Rosas	1	-7/+0
2023-01-05	target/arm: Remove unused includes from m_helper.c	Fabiano Rosas	1	-16/+0
2023-01-05	target/arm: Fix checkpatch brace errors in helper.c	Fabiano Rosas	1	-25/+42
2023-01-05	target/arm: Fix checkpatch space errors in helper.c	Fabiano Rosas	1	-21/+21
2023-01-05	target/arm: Fix checkpatch comment style warnings in helper.c	Fabiano Rosas	1	-108/+215
2023-01-05	target/arm: fix handling of HLT semihosting in system mode	Alex Bennée	1	-1/+1
2023-01-05	target/arm: Add ARM Cortex-R52 CPU	Tobias Röhmel	1	-0/+42
2023-01-05	target/arm: Add PMSAv8r functionality	Tobias Röhmel	1	-22/+104
2023-01-05	target/arm: Add PMSAv8r registers	Tobias Röhmel	4	-4/+360
2023-01-05	target/arm: Enable TTBCR_EAE for ARMv8-R AArch32	Tobias Röhmel	3	-0/+11
2023-01-05	target/arm: Make stage_2_format for cache attributes optional	Tobias Röhmel	1	-2/+8
2023-01-05	target/arm: Make RVBAR available for all ARMv8 CPUs	Tobias Röhmel	2	-8/+19
2023-01-05	target/arm: Don't add all MIDR aliases for cores that implement PMSA	Tobias Röhmel	1	-4/+9