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2018-05-17fpu/softfloat: Specialize on snan_bit_is_oneRichard Henderson4-5/+0
Only MIPS requires snan_bit_is_one to be variable. While we are specializing softfloat behaviour, allow other targets to eliminate this runtime check. Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@mips.com> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Alexander Graf <agraf@suse.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17target/s390x: Remove floatX_maybe_silence_nan from conversionsRichard Henderson1-6/+6
This is now handled properly by the generic softfloat code. Cc: Alexander Graf <agraf@suse.de> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17target/riscv: Remove floatX_maybe_silence_nan from conversionsRichard Henderson1-4/+2
This is now handled properly by the generic softfloat code. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17target/mips: Remove floatX_maybe_silence_nan from conversionsRichard Henderson2-6/+0
This is now handled properly by the generic softfloat code. Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17target/m68k: Use floatX_silence_nan when we have already checked for SNaNRichard Henderson1-1/+2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17target/hppa: Remove floatX_maybe_silence_nan from conversionsRichard Henderson1-2/+0
This is now handled properly by the generic softfloat code. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17target/arm: Remove floatX_maybe_silence_nan from conversionsRichard Henderson2-11/+2
This is now handled properly by the generic softfloat code. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17target/arm: Use floatX_silence_nan when we have already checked for SNaNRichard Henderson2-9/+9
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17target/arm: squash FZ16 behaviour for conversionsAlex Bennée1-4/+36
The ARM ARM specifies FZ16 is suppressed for conversions. Rather than pushing this logic into the softfloat code we can simply save the FZ state and temporarily disable it for the softfloat call. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17target/arm: convert conversion helpers to fpst/ahp_flagAlex Bennée5-77/+112
Instead of passing env and leaving it up to the helper to get the right fpstatus we pass it explicitly. There was already a get_fpstatus helper for neon for the 32 bit code. We also add an get_ahp_flag() for passing the state of the alternative FP16 format flag. This leaves scope for later tracking the AHP state in translation flags. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' ↵Peter Maydell2-124/+577
into staging x86 queue, 2018-05-15 * KnightsMill CPU model * CLDEMOTE(Demote Cache Line) cpu feature * pc-i440fx-2.13 and pc-q35-2.13 machine-types * Add model-specific cache information to EPYC CPU model # gpg: Signature made Tue 15 May 2018 22:53:12 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: i386: Add new property to control cache info pc: add 2.13 machine types i386: Initialize cache information for EPYC family processors i386: Add cache information in X86CPUDefinition i386: Helpers to encode cache information consistently x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature i386: add KnightsMill cpu model Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-15i386: Add new property to control cache infoBabu Moger2-26/+76
The property legacy-cache will be used to control the cache information. If user passes "-cpu legacy-cache" then older information will be displayed even if the hardware supports new information. Otherwise use the statically loaded cache definitions if available. Renamed the previous cache structures to legacy_*. If there is any change in the cache information, then it needs to be initialized in builtin_x86_defs. Signed-off-by: Babu Moger <babu.moger@amd.com> Tested-by: Geoffrey McRae <geoff@hostfission.com> Message-Id: <20180514164156.27034-3-babu.moger@amd.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-05-15i386: Initialize cache information for EPYC family processorsBabu Moger1-0/+52
Initialize pre-determined cache information for EPYC processors. Signed-off-by: Babu Moger <babu.moger@amd.com> Tested-by: Geoffrey McRae <geoff@hostfission.com> Message-Id: <20180510204148.11687-5-babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-05-15i386: Add cache information in X86CPUDefinitionBabu Moger2-0/+8
Add cache information in X86CPUDefinition and CPUX86State. Signed-off-by: Babu Moger <babu.moger@amd.com> Tested-by: Geoffrey McRae <geoff@hostfission.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180510204148.11687-3-babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-05-15i386: Helpers to encode cache information consistentlyEduardo Habkost2-124/+424
Instead of having a collection of macros that need to be used in complex expressions to build CPUID data, define a CPUCacheInfo struct that can hold information about a given cache. Helper functions will take a CPUCacheInfo struct as input to encode CPUID leaves for a cache. This will help us ensure consistency between cache information CPUID leaves, and make the existing inconsistencies in CPUID info more visible. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Tested-by: Geoffrey McRae <geoff@hostfission.com> Message-Id: <20180510204148.11687-2-babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-05-15x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu featureJingqi Liu2-1/+2
The CLDEMOTE instruction hints to hardware that the cache line that contains the linear address should be moved("demoted") from the cache(s) closest to the processor core to a level more distant from the processor core. This may accelerate subsequent accesses to the line by other cores in the same coherence domain, especially if the line was written by the core that demotes the line. Intel Snow Ridge has added new cpu feature, CLDEMOTE. The new cpu feature needs to be exposed to guest VM. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Jingqi Liu <jingqi.liu@intel.com> Message-Id: <1525406253-54846-1-git-send-email-jingqi.liu@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-05-15i386: add KnightsMill cpu modelBoqun Feng1-0/+42
A new cpu model called "KnightsMill" is added to model Knights Mill processors. Compared to "Skylake-Server" cpu model, the following features are added: avx512_4vnniw avx512_4fmaps avx512pf avx512er avx512_vpopcntdq and the following features are removed: pcid invpcid clflushopt avx512dq avx512bw clwb smap rtm mpx xsavec xgetbv1 hle Signed-off-by: Boqun Feng <boqun.feng@intel.com> Message-Id: <20180320000821.8337-1-boqun.feng@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-05-15target/arm: Fix sqrt_f16 exception raisingAlex Bennée1-1/+2
We are meant to explicitly pass fpst, not cpu_env. Cc: qemu-stable@nongnu.org Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180512003217.9105-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-15target/arm: Implement FMOV (immediate) for fp16Alex Bennée1-3/+17
All the hard work is already done by vfp_expand_imm, we just need to make sure we pick up the correct size. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180512003217.9105-11-richard.henderson@linaro.org [rth: Merge unallocated_encoding check with TCGMemOp conversion.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-15target/arm: Implement FCSEL for fp16Alex Bennée1-6/+25
These were missed out from the rest of the half-precision work. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180512003217.9105-10-richard.henderson@linaro.org [rth: Fix erroneous check vs type] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-15target/arm: Implement FCMP for fp16Alex Bennée3-17/+83
These where missed out from the rest of the half-precision work. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180512003217.9105-9-richard.henderson@linaro.org [rth: Diagnose lack of FP16 before fp_access_check] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-15target/arm: Implement FP data-processing (3 source) for fp16Richard Henderson1-0/+48
We missed all of the scalar fp16 fma operations. Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180512003217.9105-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-15target/arm: Implement FP data-processing (2 source) for fp16Richard Henderson1-0/+65
We missed all of the scalar fp16 binary operations. Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180512003217.9105-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-15target/arm: Introduce and use read_fp_hregRichard Henderson1-16/+14
Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180512003217.9105-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-15target/arm: Implement FCVT (scalar, fixed-point) for fp16Richard Henderson1-2/+15
Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180512003217.9105-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-15target/arm: Implement FCVT (scalar, integer) for fp16Richard Henderson3-18/+122
Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180512003217.9105-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-15target/arm: Early exit after unallocated_encoding in disas_fp_int_convRichard Henderson1-1/+1
No sense in emitting code after the exception. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180512003217.9105-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-15target/arm: Implement FMOV (general) for fp16Richard Henderson1-0/+21
Adding the fp16 moves to/from general registers. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180512003217.9105-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-15target/arm: Fix fp_status_f16 tininess before roundingPeter Maydell1-0/+2
In commit d81ce0ef2c4f105 we added an extra float_status field fp_status_fp16 for Arm, but forgot to initialize it correctly by setting it to float_tininess_before_rounding. This currently will only cause problems for the new V8_FP16 feature, since the float-to-float conversion code doesn't use it yet. The effect would be that we failed to set the Underflow IEEE exception flag in all the cases where we should. Add the missing initialization. Fixes: d81ce0ef2c4f105 Cc: qemu-stable@nongnu.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
2018-05-15Merge remote-tracking branch 'remotes/rth/tags/tgt-openrisc-pull-request' ↵Peter Maydell5-1151/+1050
into staging Convert openrisc to decodetree.py # gpg: Signature made Mon 14 May 2018 23:25:40 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/tgt-openrisc-pull-request: target/openrisc: Merge disas_openrisc_insn target/openrisc: Convert dec_float target/openrisc: Convert dec_compi target/openrisc: Convert dec_comp target/openrisc: Convert dec_M target/openrisc: Convert dec_logic target/openrisc: Convert dec_mac target/openrisc: Convert dec_calc target/openrisc: Convert remainder of dec_misc insns target/openrisc: Convert memory insns target/openrisc: Convert branch insns target/openrisc: Start conversion to decodetree.py target-openrisc: Write back result before FPE exception Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-14target/openrisc: Merge disas_openrisc_insnRichard Henderson1-9/+4
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_floatRichard Henderson2-230/+149
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_compiRichard Henderson2-58/+70
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_compRichard Henderson2-62/+73
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_MRichard Henderson2-28/+16
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_logicRichard Henderson2-36/+32
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_macRichard Henderson2-33/+27
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_calcRichard Henderson2-169/+229
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert remainder of dec_misc insnsRichard Henderson2-153/+141
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert memory insnsRichard Henderson2-139/+160
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert branch insnsRichard Henderson2-78/+84
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Start conversion to decodetree.pyRichard Henderson3-43/+78
Begin with the 0x08 major opcode, the system instructions. Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target-openrisc: Write back result before FPE exceptionRichard Henderson3-252/+126
The architecture manual is unclear about this, but the or1ksim does writeback before the exception. This requires splitting the helpers in half, with the exception raised by the second. Acked-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2018-05-14Merge remote-tracking branch ↵Peter Maydell1-0/+1
'remotes/vivier/tags/m68k-for-2.13-pull-request' into staging # gpg: Signature made Mon 14 May 2018 19:02:18 BST # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.13-pull-request: m68k: fix floatx80_mod() (Coverity CID1390568) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-14m68k: fix floatx80_mod() (Coverity CID1390568)Laurent Vivier1-0/+1
Update the variable checked by the loop condition (expDiff). Backport the update from Previous. Fixes: 591596b77a ("target/m68k: add fmod/frem") Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20180508203937.16796-1-laurent@vivier.eu>
2018-05-14target/s390x: Fix brace Werror with clang 6.0.0Richard Henderson1-1/+1
The warning is target/s390x/misc_helper.c:209:21: error: suggest braces around initialization of subobject [-Werror,-Wmissing-braces] SysIB sysib = { 0 }; ^ {} While the original code is correct, and technically exactly correct as per ISO C89, both GCC and Clang support plain empty set of braces as an extension. Cc: Alexander Graf <agraf@suse.de> Cc: David Hildenbrand <david@redhat.com> Cc: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180512045950.12386-5-richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-05-14s390x: refactor reset/reipl handlingDavid Hildenbrand4-64/+31
Calling pause_all_vcpus()/resume_all_vcpus() from a VCPU thread might not be the best idea. As pause_all_vcpus() temporarily drops the qemu mutex, two parallel calls to pause_all_vcpus() can be active at a time, resulting in a deadlock. (either by two VCPUs or by the main thread and a VCPU) Let's handle it via the main loop instead, as suggested by Paolo. If we would have two parallel reset requests by two different VCPUs at the same time, the last one would win. We use the existing ipl device to handle it. The nice side effect is that we can get rid of reipl_requested. This change implies that all reset handling now goes via the common path, so "no-reboot" handling is now active for all kinds of reboots. Let's execute any CPU initialization code on the target CPU using run_on_cpu. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180424101859.10239-1-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-05-14Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell14-23/+98
* Don't silently truncate extremely long words in the command line * dtc configure fixes * MemoryRegionCache second try * Deprecated option removal * add support for Hyper-V reenlightenment MSRs # gpg: Signature made Fri 11 May 2018 13:33:46 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (29 commits) rename included C files to foo.inc.c, remove osdep.h pc-dimm: fix error messages if no slots were defined build: Silence dtc directory creation shippable: Remove Debian 8 libfdt kludge configure: Display if libfdt is from system or git configure: Really use local libfdt if the system one is too old i386/kvm: add support for Hyper-V reenlightenment MSRs qemu-doc: provide details of supported build platforms qemu-options: Remove deprecated -no-kvm-irqchip qemu-options: Remove deprecated -no-kvm-pit-reinjection qemu-options: Bail out on unsupported options instead of silently ignoring them qemu-options: Remove remainders of the -tdf option qemu-options: Mark -virtioconsole as deprecated target/i386: sev: fix memory leaks opts: don't silently truncate long option values opts: don't silently truncate long parameter keys accel: use g_strsplit for parsing accelerator names update-linux-headers: drop hyperv.h qemu-thread: always keep the posix wrapper layer exec: reintroduce MemoryRegion caching ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-11Merge remote-tracking branch ↵Peter Maydell9-188/+514
'remotes/pmaydell/tags/pull-target-arm-20180510' into staging target-arm queue: * hw/arm/iotkit.c: fix minor memory leak * softfloat: fix wrong-exception-flags bug for multiply-add corner case * arm: isolate and clean up DTB generation * implement Arm v8.1-Atomics extension * Fix some bugs and missing instructions in the v8.2-FP16 extension # gpg: Signature made Thu 10 May 2018 18:44:34 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180510: (21 commits) target/arm: Clear SVE high bits for FMOV target/arm: Fix float16 to/from int16 target/arm: Implement vector shifted FCVT for fp16 target/arm: Implement vector shifted SCVF/UCVF for fp16 target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only target/arm: Implement CAS and CASP target/arm: Fill in disas_ldst_atomic target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode target/riscv: Use new atomic min/max expanders tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add tcg: Introduce atomic helpers for integer min/max target/xtensa: Use new min/max expanders target/arm: Use new min/max expanders tcg: Introduce helpers for integer min/max atomic.h: Work around gcc spurious "unused value" warning make sure that we aren't overwriting mc->get_hotplug_handler by accident arm/boot: split load_dtb() from arm_load_kernel() platform-bus-device: use device plug callback instead of machine_done notifier pc: simplify MachineClass::get_hotplug_handler handling softfloat: Handle default NaN mode after pickNaNMulAdd, not before ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/riscv/translate.c
2018-05-11Merge remote-tracking branch 'remotes/rth/tags/cota-target-pull-request' ↵Peter Maydell19-1569/+1532
into staging * Fix all next_page checks for overflow. * Convert six targets to the translator loop. # gpg: Signature made Wed 09 May 2018 18:20:43 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/cota-target-pull-request: (28 commits) target/riscv: convert to TranslatorOps target/riscv: convert to DisasContextBase target/riscv: convert to DisasJumpType target/openrisc: convert to TranslatorOps target/openrisc: convert to DisasContextBase target/s390x: convert to TranslatorOps target/s390x: convert to DisasContextBase target/s390x: convert to DisasJumpType target/mips: convert to TranslatorOps target/mips: use *ctx for DisasContext target/mips: convert to DisasContextBase target/mips: convert to DisasJumpType target/mips: use lookup_and_goto_ptr on BS_STOP target/sparc: convert to TranslatorOps target/sparc: convert to DisasContextBase target/sparc: convert to DisasJumpType target/sh4: convert to TranslatorOps translator: merge max_insns into DisasContextBase target/mips: avoid integer overflow in next_page PC check target/s390x: avoid integer overflow in next_page PC check ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2024-12-28 06:34:36 +0000