riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-05-02	target/mips: Merge do_translate_address into cpu_mips_translate_address	Philippe Mathieu-Daudé	3	-24/+9
2021-05-02	target/mips: Declare mips_env_set_pc() inlined in "internal.h"	Philippe Mathieu-Daudé	3	-20/+14
2021-05-02	target/mips: Turn printfpr() macro into a proper function	Philippe Mathieu-Daudé	1	-27/+23
2021-05-02	target/mips: Restrict mips_cpu_dump_state() to cpu.c	Philippe Mathieu-Daudé	3	-78/+77
2021-05-02	target/mips: Optimize CPU/FPU regnames[] arrays	Philippe Mathieu-Daudé	3	-4/+4
2021-05-02	target/mips: Make CPU/FPU regnames[] arrays global	Philippe Mathieu-Daudé	4	-14/+17
2021-05-02	target/mips: Move msa_reset() to new source file	Philippe Mathieu-Daudé	3	-36/+61
2021-05-02	target/mips: Move IEEE rounding mode array to new source file	Philippe Mathieu-Daudé	3	-8/+19
2021-05-02	target/mips: Simplify meson TCG rules	Philippe Mathieu-Daudé	1	-3/+2
2021-05-02	target/mips: Make check_cp0_enabled() return a boolean	Philippe Mathieu-Daudé	2	-2/+9
2021-05-02	target/mips: Migrate missing CPU fields	Philippe Mathieu-Daudé	1	-6/+15
2021-05-02	target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode	Philippe Mathieu-Daudé	1	-0/+1
2021-05-02	target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes	Philippe Mathieu-Daudé	1	-0/+2
2021-05-02	target/mips: Fix CACHEE opcode (CACHE using EVA addressing)	Philippe Mathieu-Daudé	1	-1/+3
2021-05-01	Hexagon (target/hexagon) CABAC decode bin	Taylor Simpson	6	-0/+165
2021-05-01	Hexagon (target/hexagon) load into shifted register instructions	Taylor Simpson	3	-0/+88
2021-05-01	Hexagon (target/hexagon) load and unpack bytes instructions	Taylor Simpson	5	-0/+186
2021-05-01	Hexagon (target/hexagon) bit reverse (brev) addressing	Taylor Simpson	7	-0/+50
2021-05-01	Hexagon (target/hexagon) circular addressing	Taylor Simpson	7	-23/+346
2021-05-01	Hexagon (target/hexagon) add A4_addp_c/A4_subp_c	Taylor Simpson	4	-0/+65
2021-05-01	Hexagon (target/hexagon) add A6_vminub_RdP	Taylor Simpson	4	-0/+60
2021-05-01	Hexagon (target/hexagon) add A5_ACS (vacsh)	Taylor Simpson	5	-0/+60
2021-05-01	Hexagon (target/hexagon) add F2_sfinvsqrta	Taylor Simpson	7	-1/+77
2021-05-01	Hexagon (target/hexagon) add F2_sfrecipa instruction	Taylor Simpson	7	-3/+101
2021-05-01	Hexagon (target/hexagon) compile all debug code	Taylor Simpson	6	-94/+81
2021-05-01	Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h	Taylor Simpson	1	-1/+2
2021-05-01	Hexagon (target/hexagon) cleanup reg_field_info definition	Taylor Simpson	2	-4/+3
2021-05-01	Hexagon (target/hexagon) cleanup ternary operators in semantics	Taylor Simpson	1	-6/+6
2021-05-01	Hexagon (target/hexagon) use softfloat for float-to-int conversions	Taylor Simpson	6	-259/+136
2021-05-01	Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn	Taylor Simpson	1	-17/+11
2021-05-01	Hexagon (target/hexagon) use softfloat default NaN and tininess	Taylor Simpson	2	-47/+5
2021-05-01	Hexagon (target/hexagon) change type of softfloat_roundingmodes	Taylor Simpson	1	-1/+1
2021-05-01	Hexagon (target/hexagon) remove unused carry_from_add64 function	Taylor Simpson	3	-16/+0
2021-05-01	Hexagon (target/hexagon) change variables from int to bool when appropriate	Taylor Simpson	6	-59/+60
2021-05-01	Hexagon (target/hexagon) decide if pred has been written at TCG gen time	Taylor Simpson	4	-10/+25
2021-05-01	Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN	Taylor Simpson	2	-32/+33
2021-05-01	Hexagon (target/hexagon) use env_archcpu and env_cpu	Taylor Simpson	4	-9/+4
2021-05-01	Hexagon (target/hexagon) remove unnecessary inline directives	Taylor Simpson	5	-47/+46
2021-05-01	Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair	Taylor Simpson	1	-14/+13
2021-05-01	Hexagon (target/hexagon) TCG generation cleanup	Taylor Simpson	1	-5/+9
2021-05-01	target/hexagon: remove unnecessary semicolons	Taylor Simpson	1	-2/+2
2021-05-01	target/hexagon: fix typo in comment	Taylor Simpson	1	-1/+1
2021-05-01	target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM	Taylor Simpson	1	-2/+2
2021-05-01	target/hexagon: remove unnecessary checks in find_iclass_slots	Taylor Simpson	1	-4/+0
2021-05-01	target/hexagon: translation changes	Taylor Simpson	1	-17/+9
2021-04-30	target/arm: Enforce alignment for sve LD1R	Richard Henderson	1	-1/+1
2021-04-30	target/arm: Enforce alignment for aa64 vector LDn/STn (single)	Richard Henderson	1	-4/+5
2021-04-30	target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)	Richard Henderson	1	-4/+11
2021-04-30	target/arm: Use MemOp for size + endian in aa64 vector ld/st	Richard Henderson	1	-10/+10
2021-04-30	target/arm: Enforce alignment for aa64 load-acq/store-rel	Richard Henderson	1	-9/+14