riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-02-21	target/rx: Remove unused ENV_OFFSET definition	Philippe Mathieu-Daudé	1	-2/+0
2022-02-21	target/avr: Correct AVRCPUClass docstring	Philippe Mathieu-Daudé	1	-1/+0
2022-02-18	target/ppc: Move common SPR functions out of cpu_init	Fabiano Rosas	3	-400/+403
2022-02-18	target/ppc: cpu_init: Move check_pow and QOM macros to a header	Fabiano Rosas	2	-37/+39
2022-02-18	target/ppc: cpu_init: Move SPR registration macros to a header	Fabiano Rosas	2	-56/+65
2022-02-18	target/ppc: cpu_init: Expose some SPR registration helpers	Fabiano Rosas	2	-7/+15
2022-02-18	target/ppc: Rename spr_tcg.h to spr_common.h	Fabiano Rosas	3	-4/+4
2022-02-18	target/ppc: cpu_init: Remove register_usprg3_sprs	Fabiano Rosas	1	-10/+11
2022-02-18	target/ppc: cpu_init: Rename register_ne_601_sprs	Fabiano Rosas	1	-21/+20
2022-02-18	target/ppc: cpu_init: Reuse init_proc_745 for the 755	Fabiano Rosas	1	-17/+1
2022-02-18	target/ppc: cpu_init: Reuse init_proc_604 for the 604e	Fabiano Rosas	1	-11/+1
2022-02-18	target/ppc: cpu_init: Reuse init_proc_603 for the e300	Fabiano Rosas	1	-58/+46
2022-02-18	target/ppc: cpu_init: Move 604e SPR registration into a function	Fabiano Rosas	1	-19/+24
2022-02-18	target/ppc: cpu_init: Move e300 SPR registration into a function	Fabiano Rosas	1	-29/+35
2022-02-18	target/ppc: cpu_init: Move 755 L2 cache SPRs into a function	Fabiano Rosas	1	-9/+15
2022-02-18	target/ppc: cpu_init: Deduplicate 7xx SPR registration	Fabiano Rosas	1	-57/+11
2022-02-18	target/ppc: cpu_init: Deduplicate 745/755 SPR registration	Fabiano Rosas	1	-31/+19
2022-02-18	target/ppc: cpu_init: Deduplicate 604 SPR registration	Fabiano Rosas	1	-10/+7
2022-02-18	target/ppc: cpu_init: Deduplicate 603 SPR registration	Fabiano Rosas	1	-19/+9
2022-02-18	target/ppc: cpu_init: Deduplicate 440 SPR registration	Fabiano Rosas	1	-74/+26
2022-02-18	target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx	Fabiano Rosas	1	-16/+91
2022-02-18	target/ppc: cpu_init: Decouple G2 SPR registration from 755	Fabiano Rosas	1	-5/+20
2022-02-18	target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs	Fabiano Rosas	1	-19/+22
2022-02-18	target/ppc: cpu_init: Move 405 SPRs into register_405_sprs	Fabiano Rosas	1	-11/+13
2022-02-18	target/ppc: cpu_init: Avoid nested SPR register functions	Fabiano Rosas	1	-3/+3
2022-02-18	target/ppc: cpu_init: Move Timebase registration into the common function	Fabiano Rosas	1	-80/+18
2022-02-18	target/ppc: cpu_init: Group registration of generic SPRs	Fabiano Rosas	1	-26/+32
2022-02-18	target/ppc: cpu_init: Remove G2LE init code	Fabiano Rosas	1	-41/+1
2022-02-18	target/ppc: cpu_init: Remove not implemented comments	Fabiano Rosas	1	-329/+253
2022-02-18	target/ppc: Introduce a vhyp framework for nested HV support	Nicholas Piggin	3	-13/+69
2022-02-18	target/ppc: Add powerpc_reset_excp_state helper	Nicholas Piggin	1	-20/+22
2022-02-18	target/ppc: add helper for books vhyp hypercall handler	Nicholas Piggin	1	-1/+13
2022-02-18	target/ppc: make vhyp get_pate method take lpid and return success	Nicholas Piggin	2	-2/+9
2022-02-18	target/ppc: add vhyp addressing mode helper for radix MMU	Nicholas Piggin	1	-4/+15
2022-02-18	target/ppc: raise HV interrupts for partition table entry problems	Nicholas Piggin	1	-2/+4
2022-02-16	target/riscv: add support for svpbmt extension	Weiwei Li	3	-1/+6
2022-02-16	target/riscv: add support for svinval extension	Weiwei Li	5	-0/+85
2022-02-16	target/riscv: add support for svnapot extension	Weiwei Li	3	-3/+18
2022-02-16	target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE	Weiwei Li	1	-0/+3
2022-02-16	target/riscv: Ignore reserved bits in PTE for RV64	Guo Ren	3	-1/+30
2022-02-16	target/riscv: Allow users to force enable AIA CSRs in HART	Anup Patel	2	-0/+6
2022-02-16	target/riscv: Implement AIA IMSIC interface CSRs	Anup Patel	1	-0/+203
2022-02-16	target/riscv: Implement AIA xiselect and xireg CSRs	Anup Patel	3	-0/+187
2022-02-16	target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs	Anup Patel	1	-0/+156
2022-02-16	target/riscv: Implement AIA interrupt filtering CSRs	Anup Patel	1	-0/+23
2022-02-16	target/riscv: Implement AIA hvictl and hviprioX CSRs	Anup Patel	3	-1/+131
2022-02-16	target/riscv: Implement AIA CSRs for 64 local interrupts on RV32	Anup Patel	4	-120/+474
2022-02-16	target/riscv: Implement AIA local interrupt priorities	Anup Patel	4	-21/+294
2022-02-16	target/riscv: Allow AIA device emulation to set ireg rmw callback	Anup Patel	2	-0/+37
2022-02-16	target/riscv: Add defines for AIA CSRs	Anup Patel	1	-0/+119