riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-08-24	target/arm: Separate decode from handling of coproc insns	Peter Maydell	1	-32/+44
2020-08-24	target/arm: Pull handling of XScale insns out of disas_coproc_insn()	Peter Maydell	1	-15/+29
2020-08-24	target/microblaze: mbar: Trap sleeps from user-space	Edgar E. Iglesias	1	-0/+5
2020-08-24	target/microblaze: swx: Use atomic_cmpxchg	Edgar E. Iglesias	1	-8/+13
2020-08-24	target/microblaze: mbar: Add support for data-access barriers	Edgar E. Iglesias	1	-0/+5
2020-08-24	target/microblaze: mbar: Move LOG_DIS to before sleep	Edgar E. Iglesias	1	-1/+2
2020-08-24	target/microblaze: mbar: Transfer dc->rd to mbar_imm	Edgar E. Iglesias	1	-2/+4
2020-08-24	Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.2-20200818' into...	Peter Maydell	8	-54/+197
2020-08-23	Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...	Peter Maydell	8	-83/+245
2020-08-21	target/riscv: Change the TLB page size depends on PMP entries.	Zong Li	3	-2/+62
2020-08-21	target/riscv: Fix the translation of physical address	Zong Li	1	-2/+3
2020-08-21	riscv: Fix bug in setting pmpcfg CSR for RISCV64	Hou Weiying	1	-3/+2
2020-08-21	target/riscv: check before allocating TCG temps	LIU Zhiwei	2	-8/+8
2020-08-21	target/riscv: Clean up fmv.w.x	LIU Zhiwei	1	-5/+1
2020-08-21	target/riscv: Check nanboxed inputs in trans_rvf.inc.c	Richard Henderson	2	-16/+73
2020-08-21	target/riscv: Check nanboxed inputs to fp helpers	Richard Henderson	2	-18/+57
2020-08-21	target/riscv: Generate nanboxed results from trans_rvf.inc.c	Richard Henderson	1	-0/+4
2020-08-21	target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s	Richard Henderson	2	-15/+12
2020-08-21	target/riscv: Generate nanboxed results from fp helpers	Richard Henderson	2	-19/+28
2020-08-21	target/xtensa: import DSP3400 core	Max Filippov	6	-0/+173129
2020-08-21	target/xtensa: import de233_fpu core	Max Filippov	6	-0/+22538
2020-08-21	target/xtensa: implement FPU division and square root	Max Filippov	3	-0/+132
2020-08-21	target/xtensa: add DFPU registers and opcodes	Max Filippov	6	-34/+1413
2020-08-21	target/xtensa: add DFPU option	Max Filippov	2	-0/+25
2020-08-21	target/xtensa: don't access BR regfile directly	Max Filippov	3	-34/+42
2020-08-21	target/xtensa: move FSR/FCR register accessors	Max Filippov	1	-32/+32
2020-08-21	target/xtensa: rename FPU2000 translators and helpers	Max Filippov	3	-55/+57
2020-08-21	target/xtensa: support copying registers up to 64 bits wide	Max Filippov	2	-5/+22
2020-08-21	target/xtensa: add geometry to xtensa_get_regfile_by_name	Max Filippov	3	-10/+31
2020-08-21	target/xtensa: implement NMI support	Max Filippov	3	-9/+21
2020-08-21	target/xtensa: make opcode properties more dynamic	Max Filippov	2	-265/+278
2020-08-21	target/s390x: fix meson.build issue	Paolo Bonzini	1	-1/+1
2020-08-21	meson: link emulators without Makefile.target	Paolo Bonzini	1	-0/+13
2020-08-21	meson: target	Paolo Bonzini	57	-320/+575
2020-08-21	meson: convert target/s390x/gen-features.h	Marc-André Lureau	5	-22/+12
2020-08-21	meson: rename .inc.h files to .h.inc	Paolo Bonzini	3	-2/+2
2020-08-21	meson: rename included C source files to .c.inc	Paolo Bonzini	67	-95/+95
2020-08-21	trace: switch position of headers to what Meson requires	Paolo Bonzini	8	-0/+8
2020-08-13	target/ppc: Integrate icount to purr, vtb, and tbu40	Gustavo Romero	1	-0/+30
2020-08-12	target/ppc: Fix SPE unavailable exception triggering	Matthieu Bucchianeri	1	-33/+64
2020-08-12	target/ppc: add vmulh{su}d instructions	Lijun Pan	4	-0/+22
2020-08-12	target/ppc: add vmulh{su}w instructions	Lijun Pan	4	-2/+29
2020-08-12	target/ppc: add vmulld instruction	Lijun Pan	2	-0/+5
2020-08-12	target/ppc: convert vmuluwm to tcg_gen_gvec_mul	Lijun Pan	3	-15/+1
2020-08-12	target/ppc: add byte-reverse br[dwh] instructions	Lijun Pan	1	-0/+40
2020-08-12	target/ppc: Enable Power ISA 3.1	Lijun Pan	2	-2/+2
2020-08-12	target/ppc: Introduce Power ISA 3.1 flag	Lijun Pan	1	-0/+2
2020-08-12	target/ppc: Fix TCG leak with the evmwsmiaa instruction	Matthieu Bucchianeri	1	-2/+2
2020-08-05	target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64	Peter Maydell	1	-1/+91
2020-08-05	target/riscv/vector_helper: Fix build on 32-bit big endian hosts	Thomas Huth	1	-2/+2