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2022-07-14Merge tag 'darwin-20220712' of https://github.com/philmd/qemu into stagingPeter Maydell3-13/+23
Darwin patches: - Enable RDTSCP support on HVF - ui/cocoa: Take refresh rate into account Few buildsys fixes: - Restrict TCG to emulation - Remove a unused-but-set-variable warning - Allow running Avocado from pseudo-"in source tree" builds # gpg: Signature made Tue 12 Jul 2022 23:14:37 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'darwin-20220712' of https://github.com/philmd/qemu: avocado: Fix BUILD_DIR if it's equal to SOURCE_DIR ui/cocoa: Take refresh rate into account ui/cocoa: Fix switched_to_fullscreen warning configure: Restrict TCG to emulation hvf: Enable RDTSCP support Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-13hvf: Enable RDTSCP supportCameron Esfahani3-13/+23
Pass through RDPID and RDTSCP support in CPUID if host supports it. Correctly detect if CPU_BASED_TSC_OFFSET and CPU_BASED2_RDTSCP would be supported in primary and secondary processor-based VM-execution controls. Enable RDTSCP in secondary processor controls if RDTSCP support is indicated in CPUID. Signed-off-by: Cameron Esfahani <dirty@apple.com> Message-Id: <20220214185605.28087-7-f4bug@amsat.org> Tested-by: Silvio Moioli <moio@suse.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1011 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Remove GET_TARGET_STRING and FREE_TARGET_STRINGRichard Henderson1-18/+9
Inline these macros into the only two callers. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220628111701.677216-9-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Simplify UHI_argnlen and UHI_argnRichard Henderson1-23/+21
With semihosting_get_arg, we already have a check vs argc, so there's no point replicating it -- just check the result vs NULL. Merge copy_argn_to_target into its caller. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220628111701.677216-8-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Use error_report for UHI_assertRichard Henderson1-21/+18
Always log the assert locally. Do not report_fault, but instead include the fact of the fault in the assertion. Don't bother freeing allocated strings before the abort(). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220628111701.677216-6-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Avoid qemu_semihosting_log_out for UHI_plogRichard Henderson1-11/+41
Use semihost_sys_write and/or qemu_semihosting_console_write for implementing plog. When using gdbstub, copy the temp string below the stack so that gdb has a guest address from which to perform the log. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220628111701.677216-5-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Use semihosting/syscalls.hRichard Henderson1-120/+91
This separates guest file descriptors from host file descriptors, and utilizes shared infrastructure for integration with gdbstub. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220628111701.677216-4-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Drop link syscall from semihostingRichard Henderson1-9/+0
We don't implement it with _WIN32 hosts, and the syscall is missing from the gdb remote file i/o interface. Since we can't implement it universally, drop it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220628111701.677216-3-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Create report_fault for semihostingRichard Henderson1-18/+15
The UHI specification does not have an EFAULT value, and further specifies that "undefined UHI operations should not return control to the target". So, log the error and abort. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220628111701.677216-2-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: introduce Cavium Octeon CPU modelPavel Dovgalyuk1-0/+28
This patch adds Cavium Octeon 68XX vCPU which provides Octeon-specific instructions. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Message-Id: <165572673785.167724.7604881144978983510.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: implement Octeon-specific arithmetic instructionsPavel Dovgalyuk2-0/+181
This patch implements several Octeon-specific instructions: - BADDU - DMUL - EXTS/EXTS32 - CINS/CINS32 - POP/DPOP - SEQ/SEQI - SNE/SNEI Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572673245.167724.17377788816335619000.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: implement Octeon-specific BBIT instructionsPavel Dovgalyuk2-0/+39
This patch introduces Octeon-specific decoder and implements check-bit-and-jump instructions. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572672705.167724.16667636081912075906.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: introduce decodetree structure for Cavium Octeon extensionPavel Dovgalyuk6-0/+31
This patch adds decodetree for Cavium Octeon extension and an instruction set extension flag for using it in CPU models. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572672162.167724.13656301229517693806.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-11target/arm: Enable SME for user-onlyRichard Henderson1-0/+11
Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-45-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Only set ZEN in reset if SVE presentRichard Henderson1-4/+3
There's no reason to set CPACR_EL1.ZEN if SVE disabled. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-44-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Enable SME for -cpu maxRichard Henderson1-0/+11
Note that SME remains effectively disabled for user-only, because we do not yet set CPACR_EL1.SMEN. This needs to wait until the kernel ABI is implemented. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-33-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Reset streaming sve state on exception boundariesRichard Henderson1-2/+13
We can handle both exception entry and exception return by hooking into aarch64_sve_change_el. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement SCLAMP, UCLAMPRichard Henderson4-0/+149
This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement REVDRichard Henderson4-0/+21
This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement PSELRichard Henderson2-0/+77
This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement SME integer outer productRichard Henderson4-0/+118
This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement FMOPA, FMOPS (widening)Richard Henderson4-0/+78
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement BFMOPA, BFMOPSRichard Henderson4-0/+90
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement FMOPA, FMOPS (non-widening)Richard Henderson4-0/+115
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement SME ADDHA, ADDVARichard Henderson4-0/+137
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement SME LDR, STRRichard Henderson2-0/+31
We can reuse the SVE functions for LDR and STR, passing in the base of the ZA vector and a zero offset. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Export unpredicated ld/st from translate-sve.cRichard Henderson2-12/+39
Add a TCGv_ptr base argument, which will be cpu_env for SVE. We will reuse this for SME save and restore array insns. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement SME LD1, ST1Richard Henderson4-0/+756
We cannot reuse the SVE functions for LD[1-4] and ST[1-4], because those functions accept only a Zreg register number. For SME, we want to pass a pointer into ZA storage. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement SME MOVARichard Henderson8-1/+331
We can reuse the SVE functions for implementing moves to/from horizontal tile slices, but we need new ones for moves to/from vertical tile slices. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement SME ZERORichard Henderson4-0/+44
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Implement SME RDSVL, ADDSVL, ADDSPLRichard Henderson3-1/+54
These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Handle SME in sve_access_checkRichard Henderson1-6/+16
The pseudocode for CheckSVEEnabled gains a check for Streaming SVE mode, and for SME present but SVE absent. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Add SME enablement checksRichard Henderson2-0/+55
These functions will be used to verify that the cpu is in the correct state for a given instruction. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark LD1RO as non-streamingRichard Henderson2-3/+2
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark LDFF1 and LDNF1 as non-streamingRichard Henderson2-2/+2
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark gather prefetch as non-streamingRichard Henderson3-8/+16
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. In this case, introduce PRF_ns (prefetch non-streaming) to handle the checks. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark gather/scatter load/store as non-streamingRichard Henderson2-9/+6
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark string/histo/crypto as non-streamingRichard Henderson2-18/+18
Mark these as non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark SMMLA, UMMLA, USMMLA as non-streamingRichard Henderson2-7/+6
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark FTSMUL, FTMAD, FADDA as non-streamingRichard Henderson2-7/+11
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark PMULL, FMMLA as non-streamingRichard Henderson2-11/+15
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streamingRichard Henderson2-13/+12
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark RDFFR, WRFFR, SETFFR as non-streamingRichard Henderson2-5/+6
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark ADR as non-streamingRichard Henderson3-5/+11
Mark ADR as a non-streaming instruction, which should trap if full a64 support is not enabled in streaming mode. Removing entries from sme-fa64.decode is an easy way to see what remains to be done. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Trap non-streaming usage when Streaming SVE is activeRichard Henderson8-2/+195
This new behaviour is in the ARM pseudocode function AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which the trap would be delivered is in AArch64 mode. Given that ARMv9 drops support for AArch32 outside EL0, the trap EL detection ought to be trivially true, but the pseudocode still contains a number of conditions, and QEMU has not yet committed to dropping A32 support for EL[12] when v9 features are present. Since the computation of SME_TRAP_NONSTREAMING is necessarily different for the two modes, we might as well preserve bits within TBFLAG_ANY and allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead. Note that DDI0616A.a has typos for bits [22:21] of LD1RO in the table of instructions illegal in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Add infrastructure for disas_smeRichard Henderson5-1/+64
This includes the build rules for the decoder, and the new file for translation, but excludes any instructions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Handle SME in aarch64_cpu_dump_stateRichard Henderson1-1/+16
Dump SVCR, plus use the correct access check for Streaming Mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-08Merge tag 'pull-target-arm-20220707' of ↵Richard Henderson9-514/+637
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm/virt: dt: add rng-seed property * Fix MTE check in sve_ldnfff1_r * Record tagged bit for user-only in sve_probe_page * Correctly implement OS Lock and OS DoubleLock * Implement DBGDEVID, DBGDEVID1, DBGDEVID2 registers * Fix qemu-system-arm handling of LPAE block descriptors for highmem # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmLG0O8ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3h1MEACnTd+jfssa/MdtQPP8N+cp # cvrdrW+V9iho1vLPGG3d6yni6T8IMdulA5OvSkiNz2IaspY3z3u/t01PCpqEF0tA # nl3HxA65ddehzG8QHpORiP2DIJfuYUcMaruK2zMcC//0EXBOVI215hkR7oNyC0r9 # PrYb+tiDVL1t3xzXWNKMoolZwUjS6M6dloxEu2b/d0tOBvtBLI0E7y9taANHCnmZ # 8r7ih0WRELo1rzveZVOXqnZGLUjFzbCurHCmshN6xr2V6iilBaLoaGHovZ2c489Z # Fz/Ui1tyvDUoajr/Ck57GYo0BwDf9dKYkl5RkchdeY+cA88CgJAVK5pT0Rrybpf0 # lMgSAalIFcnIr2kjdnWRUqL02t+HgnOnsBTSUpgiwMNKwjfMN5NDi9294GuMCu2h # 7UyuAkQvfTwoQyFzJYzuapcnB6i5BvQjq6GxSmogzuR6kNSFptNOGimMhqCO4kN0 # fixOHOOE/aj7QoXq33V9u3ESY1IleDMX6+Zff2RLmVQYZpQKW6LpCfuwgnZrZEN3 # 4hPiL+00bY9pWlXvvEHdu0/XYx8kPXtmdzgzpm80edCLUMFOVMDQMQE1Zy/qzC7S # 8ryfC2EvSQuigD1+s6I9WxCnHVv5Byz+DXgRCjRsitDPVu2kFcEgAibzz9K1WVUW # qwQP4WGUzFD/LNUwO/Vryw== # =TzwD # -----END PGP SIGNATURE----- # gpg: Signature made Thu 07 Jul 2022 05:56:23 PM +0530 # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220707' of https://git.linaro.org/people/pmaydell/qemu-arm: target/arm: Fix qemu-system-arm handling of LPAE block descriptors for highmem target/arm: Correctly implement Feat_DoubleLock target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2 target/arm: Suppress debug exceptions when OS Lock set target/arm: Move define_debug_regs() to debug_helper.c target/arm: Fix code style issues in debug helper functions target/arm: Record tagged bit for user-only in sve_probe_page target/arm: Fix MTE check in sve_ldnfff1_r hw/arm/virt: dt: add rng-seed property Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-07Merge tag 'pull-request-2022-07-07' of https://gitlab.com/thuth/qemu into ↵Richard Henderson2-25/+24
staging * Check validity of the address in the SET PREFIX instruction * Fix booting from devices that use 4k sectors, but are not like DASDs * Re-evaluate pending interrupts after EXECUTE of certain instructions # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmLGhkURHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbU76Q//Y4mEXxWZDpJTg7tL5SZP+UzBVttnCifv # 6q+2I0keOUs6wFhPq8TzBqkazT9wlv51cNrY2Q3fU9I3dpDeRbAXZR34UD4kw5an # Q+ZQcebuGSKLjzMrIb1DLAieq8OmZR5FvDUu16BbeJr6GIQIE80lMRfWh9j30UfW # tlxkXr15BnyPx6m0rSGwzkZD2vgfj5zSUrDtYJcUsfypIA9OOBMA7yNGNlO+d94V # UZiKgNQtAoBNm4hZh2M86nsUtem+WpMTZQnDnCpMLYvFV/u9jRQBFSR+Ay41hcEN # WYuLK61rkjc9gPWSjeNNT28x8RMvFJU4YNn1UDiMRSzrigxeui6MOW3SI/h3y6tI # 94yXmXV2IuDMibvOjK07nkDaEItqPxfj6zuM2xW1Nc+l8Sk12korFBpk/AZiD0Jo # R3u36efci3zNqDRDJvhGUv8sGcv0mwO7Agq1Bm3h5941gYwzQKILHCShL7DPzvQa # h+K1MsT7vWfh5++unkGUrN/Zd9CazEylbDuWtywK8lgQcTGDO/9rab8GeXfH/5es # Tp0RGJwxmalgrAHZPK9lqgpQaGw92ct2G5odvc82EXQhgccnN9mh54BHPfdKs95E # JZVrXtZH3Gtgl5MGZ+yJevWSc9h1iRnRF4a7QC3UlVBjA/9yAWzQUAnNGZOamE/s # F+pi89oWLn8= # =UsTi # -----END PGP SIGNATURE----- # gpg: Signature made Thu 07 Jul 2022 12:37:49 PM +0530 # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [undefined] # gpg: aka "Thomas Huth <thuth@redhat.com>" [undefined] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-07-07' of https://gitlab.com/thuth/qemu: target/s390x: Exit tb after executing ex_value target/s390x: Remove DISAS_PC_STALE_NOCHAIN target/s390x: Remove DISAS_PC_STALE target/s390x: Remove DISAS_GOTO_TB pc-bios/s390-ccw: Update the s390-ccw bios binaries with the virtio-blk fixes pc-bios/s390-ccw/netboot.mak: Ignore Clang's warnings about GNU extensions pc-bios/s390-ccw/virtio: Remove "extern" keyword from prototypes pc-bios/s390-ccw/virtio-blkdev: Request the right feature bits pc-bios/s390-ccw: Split virtio-scsi code from virtio_blk_setup_device() pc-bios/s390-ccw/virtio: Beautify the code for reading virtqueue configuration pc-bios/s390-ccw/virtio: Read device config after feature negotiation pc-bios/s390-ccw/virtio: Set missing status bits while initializing pc-bios/s390-ccw/virtio-blkdev: Remove virtio_assume_scsi() pc-bios/s390-ccw/virtio-blkdev: Simplify/fix virtio_ipl_disk_is_valid() pc-bios/s390-ccw/bootmap: Improve the guessing logic in zipl_load_vblk() pc-bios/s390-ccw/virtio: Introduce a macro for the DASD block size pc-bios/s390-ccw: Add a proper prototype for main() target/s390x/tcg: SPX: check validity of new prefix Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-07target/arm: Fix qemu-system-arm handling of LPAE block descriptors for highmemPeter Maydell1-1/+1
In commit 39a1fd25287f5d we fixed a bug in the handling of LPAE block descriptors where we weren't correctly zeroing out some RES0 bits. However this fix has a bug because the calculation of the mask is done at the wrong width: in descaddr &= ~(page_size - 1); page_size is a target_ulong, so in the 'qemu-system-arm' binary it is only 32 bits, and the effect is that we always zero out the top 32 bits of the calculated address. Fix the calculation by forcing the mask to be calculated with the same type as descaddr. This only affects 32-bit CPUs which support LPAE (e.g. cortex-a15) when used on board models which put RAM or devices above the 4GB mark and when the 'qemu-system-arm' executable is being used. It was also masked in 7.0 by the main bug reported in https://gitlab.com/qemu-project/qemu/-/issues/1078 where the virt board incorrectly does not enable 'highmem' for 32-bit CPUs. The workaround is to use 'qemu-system-aarch64' with the same command line. Reported-by: He Zhe <zhe.he@windriver.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220627134620.3190252-1-peter.maydell@linaro.org Fixes: 39a1fd25287f5de ("target/arm: Fix handling of LPAE block descriptors") Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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