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2018-07-10target/arm: Use correct mmu_idx for exception-return unstackingPeter Maydell1-1/+3
For M-profile exception returns, the mmu index to use for exception return unstacking is supposed to be that of wherever we are returning to: * if returning to handler mode, privileged * if returning to thread mode, privileged or unprivileged depending on CONTROL.nPRIV for the destination security state We were passing the wrong thing as the 'priv' argument to arm_v7m_mmu_idx_for_secstate_and_priv(). The effect was that guests which programmed the MPU to behave differently for privileged and unprivileged code could get spurious MemManage Unstack exceptions. Reported-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180709124535.1116-1-peter.maydell@linaro.org
2018-07-09target/sh4: Fix translator.c assertion failure for gUSARichard Henderson1-37/+44
The translator loop does not allow the tb_start hook to set dc->base.is_jmp; the only hook allowed to do that is translate_insn. Split the work between init_disas_context where we validate the gUSA parameters, and translate_insn where we emit code. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-07-09target/arm: Fix do_predset for large VLRichard Henderson1-8/+2
Use MAKE_64BIT_MASK instead of open-coding. Remove an odd vector size check that is unlikely to be more profitable than 3 64-bit integer stores. Correct the iteration for WORD to avoid writing too much data. Fixes RISU tests of PTRUE for VL 256. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180705191929.30773-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-09target/arm: Suppress Coverity warning for PRFRichard Henderson1-2/+2
These instructions must perform the sve_access_check, but since they are implemented as NOPs there is no generated code to elide when the access check fails. Fixes: Coverity issues 1393780 & 1393779. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-07target/ppc: fix build on ppc64 hostLaurent Vivier1-1/+1
When I try to build a ppc64 target on a ppc64 host (gcc 8.1.1), I have: .../target/ppc/int_helper.c: In function 'helper_vinsertb': .../target/ppc/int_helper.c:1954:32: error: array subscript 18446744073709551608 is above array bounds of 'uint8_t[16]' {aka 'unsigned char[16]'} [-Werror=array-bounds] memmove(&r->u8[index], &b->u8[8 - sizeof(r->element)], \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .../target/ppc/int_helper.c:1965:1: note: in expansion of macro 'VINSERT' If we compare with the macro for ppc64le, we can see sizeof(r->element[0]) should be used instead of sizeof(r->element). And VINSERT uses only u8, u16, u32 and u64, so the maximum value of sizeof(r->element[0]) is 8 Suggested-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-06i386: fix '-cpu ?' output for host cpu typeGreg Kurz1-7/+7
Since commit d6dcc5583e7, '-cpu ?' shows the description of the X86_CPU_TYPE_NAME("max") for the host CPU model: Enables all features supported by the accelerator in the current host instead of the expected: KVM processor with all supported host features or HVF processor with all supported host features This is caused by the early use of kvm_enabled() and hvf_enabled() in a class_init function. Since the accelerator isn't configured yet, both helpers return false unconditionally. A QEMU binary will only be compiled with one of these accelerators, not both. The appropriate description can thus be decided at build time. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <153055056654.212317.4697363278304826913.stgit@bahia.lan> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-07-03Merge remote-tracking branch 'remotes/shorne/tags/pull-or-20180703' into stagingPeter Maydell12-595/+502
OpenRISC cleanups and Fixes for QEMU 3.0 Mostly patches from Richard Henderson fixing multiple things: * Fix singlestepping in GDB. * Use more TB linking. * Fixes to exit TB after updating SPRs to enable registering of state changes. * Significant optimizations and refactors to the TLB * Split out disassembly from translation. * Add qemu-or1k to qemu-binfmt-conf.sh. * Implement signal handling for linux-user. Then there are a few fixups from me: * Fix delay slot detections to match hardware, this was masking a bug in the linus kernel. * Fix stores to the PIC mask register # gpg: Signature made Tue 03 Jul 2018 14:44:10 BST # gpg: using RSA key C3B31C2D5E6627E4 # gpg: Good signature from "Stafford Horne <shorne@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25 EFF1 C3B3 1C2D 5E66 27E4 * remotes/shorne/tags/pull-or-20180703: (25 commits) target/openrisc: Fix writes to interrupt mask register target/openrisc: Fix delay slot exception flag to match spec linux-user: Fix struct sigaltstack for openrisc linux-user: Implement signals for openrisc target/openrisc: Add support in scripts/qemu-binfmt-conf.sh target/openrisc: Reorg tlb lookup target/openrisc: Increase the TLB size target/openrisc: Stub out handle_mmu_fault for softmmu target/openrisc: Use identical sizes for ITLB and DTLB target/openrisc: Fix cpu_mmu_index target/openrisc: Fix tlb flushing in mtspr target/openrisc: Reduce tlb to a single dimension target/openrisc: Merge mmu_helper.c into mmu.c target/openrisc: Remove indirect function calls for mmu target/openrisc: Merge tlb allocation into CPUOpenRISCState target/openrisc: Form the spr index from tcg target/openrisc: Exit the TB after l.mtspr target/openrisc: Split out is_user target/openrisc: Link more translation blocks target/openrisc: Fix singlestep_enabled ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-03Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180703' ↵Peter Maydell9-341/+541
into staging ppc patch queue 2018-07-03 Here's a last minue pull request before today's soft freeze. Ideally I would have sent this earlier, but I was waiting for a couple of extra fixes I knew were close. And the freeze crept up on me, like always. Most of the changes here are bugfixes in any case. There are some cleanups as well, which have been in my staging tree for a little while. There are a couple of truly new features (some extensions to the sam460ex platform), but these are low risk, since they only affect a new and not really stabilized machine type anyway. Higlights are: * Mac platform improvements from Mark Cave-Ayland * Sam460ex improvements from BALATON Zoltan et al. * XICS interrupt handler cleanups from Cédric Le Goater * TCG improvements for atomic loads and stores from Richard Henderson * Assorted other bugfixes # gpg: Signature made Tue 03 Jul 2018 06:55:22 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-3.0-20180703: (35 commits) ppc: Include vga cirrus card into the compiling process target/ppc: Relax reserved bitmask of indexed store instructions target/ppc: set is_jmp on ppc_tr_breakpoint_check spapr: compute default value of "hpt-max-page-size" later target/ppc/kvm: don't pass cpu to kvm_get_smmu_info() target/ppc/kvm: get rid of kvm_get_fallback_smmu_info() ppc440_uc: Basic emulation of PPC440 DMA controller sam460ex: Add RTC device hw/timer: Add basic M41T80 emulation ppc4xx_i2c: Rewrite to model hardware more closely hw/ppc: Give sam46ex its own config option fpu_helper.c: fix setting FPSCR[FI] bit target/ppc: Implement the rest of gen_st_atomic target/ppc: Implement the rest of gen_ld_atomic target/ppc: Use atomic min/max helpers target/ppc: Use MO_ALIGN for EXIWX and ECOWX target/ppc: Split out gen_st_atomic target/ppc: Split out gen_ld_atomic target/ppc: Split out gen_load_locked target/ppc: Tidy gen_conditional_store ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/ppc/spapr.c
2018-07-03target/openrisc: Fix writes to interrupt mask registerStafford Horne1-1/+1
The interrupt controller mask register (PICMR) allows writing any value to any of the 32 interrupt mask bits. Writing a 0 masks the interrupt writing a 1 unmasks (enables) the the interrupt. For some reason the old code was or'ing the write values to the PICMR meaning it was not possible to ever mask a interrupt once it was enabled. I have tested this by running linux 4.18 and my regular checks, I don't see any issues. Reported-by: Davidson Francis <davidsondfgl@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Fix delay slot exception flag to match specStafford Horne1-7/+12
The delay slot exception flag is only set on the SR register during exception. Previously it was being set on both the ESR and SR this caused QEMU to differ from the spec. The was apparent as the linux kernel had a bug where it could boot on QEMU but not on real hardware. The fixed logic now matches hardware. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03linux-user: Implement signals for openriscRichard Henderson1-0/+1
All of the existing code was boilerplate from elsewhere, and would crash the guest upon the first signal. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com> --- v2: Add a comment to the new definition of target_pt_regs. Install the signal mask into the ucontext. v3: Incorporate feedback from Laurent.
2018-07-03target/openrisc: Reorg tlb lookupRichard Henderson2-170/+88
While openrisc has a split i/d tlb, qemu does not. Perform a lookup on both i & d tlbs in parallel and put the composite rights into qemu's tlb. This avoids ping-ponging the qemu tlb between EXEC and READ. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/ppc: Relax reserved bitmask of indexed store instructionsBALATON Zoltan1-1/+1
The PPC440 User Manual says that if bit 31 is set, the contents of CR[CR0] are undefined for indexed store instructions but this form is not invalid. Other PPC variants confirming to recent ISA where this bit may be reserved should ignore reserved bits and not raise invalid instruction exception. In particular, MorphOS has an stwx instruction with bit 31 set and fails to boot currently because of this. With this patch it gets further. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: set is_jmp on ppc_tr_breakpoint_checkEmilio G. Cota1-0/+1
The use of GDB breakpoints was broken by b0c2d52 ("target/ppc: convert to TranslatorOps", 2018-02-16). Fix it by setting is_jmp, so that we break from the translation loop as originally intended. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc/kvm: don't pass cpu to kvm_get_smmu_info()Greg Kurz1-9/+8
In a future patch the machine code will need to retrieve the MMU information from KVM during machine initialization before the CPUs are created. Actually, KVM_PPC_GET_SMMU_INFO is a VM class ioctl, and thus, we don't need to have a CPU object around. We just need for KVM to be initialized and use the kvm_state global. This patch just does that. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc/kvm: get rid of kvm_get_fallback_smmu_info()Greg Kurz1-97/+20
Now that we're checking our MMU configuration is supported by KVM, rather than adjusting it to KVM, it doesn't really make sense to have a fallback for kvm_get_smmu_info(). If KVM is too old or buggy to provide the details, we should rather treat this as an error. This patch thus adds error reporting to kvm_get_smmu_info() and get rid of the fallback code. QEMU will now terminate if KVM fails to provide MMU details. This may break some very old setups, but the simplification is worth the sacrifice. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03fpu_helper.c: fix setting FPSCR[FI] bitJohn Arbuckle1-0/+8
The FPSCR[FI] bit indicates if the last floating point instruction had a result that was rounded. Each consecutive floating point instruction is suppose to set this bit to the correct value. What currently happens is this bit is not set as often as it should be. I have verified that this is the behavior of a real PowerPC 950. This patch fixes that problem by deciding to set this bit after each floating point instruction. https://www.pdfdrive.net/powerpc-microprocessor-family-the-programming-environments-for-32-e3087633.html Page 63 in table 2-4 is where the description of this bit can be found. Signed-off-by: John Arbuckle <programmingkidx@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Implement the rest of gen_st_atomicRichard Henderson1-1/+25
The store twin case was stubbed out. For now, implement it only within a serial context, forcing parallel execution to synchronize. It would be possible to implement with a cmpxchg loop, if we care, but the loose alignment requirements (simply no crossing 32-byte boundary) might send us back to the serial context anyway. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Implement the rest of gen_ld_atomicRichard Henderson1-4/+79
These cases were stubbed out. For now, implement them only within a serial context, forcing parallel execution to synchronize. It would be possible to implement these with cmpxchg loops, if we care. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Use atomic min/max helpersRichard Henderson1-3/+19
These operations were previously unimplemented for ppc. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Use MO_ALIGN for EXIWX and ECOWXRichard Henderson1-21/+4
This avoids the need for gen_check_align entirely. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Split out gen_st_atomicRichard Henderson1-48/+49
Move the guts of ST_ATOMIC to a function. Use foo_tl for the operations instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an explicit call to gen_check_align. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Split out gen_ld_atomicRichard Henderson1-53/+52
Move the guts of LD_ATOMIC to a function. Use foo_tl for the operations instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an explicit call to gen_check_align. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Split out gen_load_lockedRichard Henderson1-17/+18
Leave only the minimal amount of code within the LDAR macro, moving the rest of the code into gen_load_locked. Use MO_ALIGN and remove the explicit call to gen_check_align. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Tidy gen_conditional_storeRichard Henderson1-17/+11
Leave only the minimal amount of code within the STCX macro, moving the rest of the code into gen_conditional_store. Remove the explicit call to gen_check_align; the matching LDAX will have already checked alignment, and we verify the same address. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Remove POWERPC_EXCP_STCXRichard Henderson2-19/+0
Always use the gen_conditional_store implementation that uses atomic_cmpxchg. Make sure and clear reserve_addr across most interrupts crossing the cpu_loop. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Use atomic cmpxchg for STQCXRichard Henderson3-33/+100
When running in a parallel context, we must use a helper in order to perform the 128-bit atomic operation. When running in a serial context, do the compare before the store. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Use atomic store for STQRichard Henderson3-8/+45
Section 1.4 of the Power ISA v3.0B states that this insn is single-copy atomic. As we cannot (yet) issue 128-bit stores within TCG, use the generic helpers provided. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Use atomic load for LQ and LQARXRichard Henderson4-25/+94
Section 1.4 of the Power ISA v3.0B states that both of these instructions are single-copy atomic. As we cannot (yet) issue 128-bit loads within TCG, use the generic helpers provided. Since TCG cannot (yet) return a 128-bit value, add a slot within CPUPPCState for returning the high half of a 128-bit return value. This solution is preferred to the helper assigning to architectural registers directly, as it avoids clobbering all TCG live values. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Add do_unaligned_access hookRichard Henderson3-1/+23
This allows faults from MO_ALIGN to have the same effect as from gen_check_align. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-02Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell12-48/+350
* IEC units series (Philippe) * Hyper-V PV TLB flush (Vitaly) * git archive detection (Daniel) * host serial passthrough fix (David) * NPT support for SVM emulation (Jan) * x86 "info mem" and "info tlb" fix (Doug) # gpg: Signature made Mon 02 Jul 2018 16:18:21 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (50 commits) tcg: simplify !CONFIG_TCG handling of tb_invalidate_* i386/monitor.c: make addresses canonical for "info mem" and "info tlb" target-i386: Add NPT support serial: Open non-block bsd-user: Use the IEC binary prefix definitions linux-user: Use the IEC binary prefix definitions tests/crypto: Use the IEC binary prefix definitions vl: Use the IEC binary prefix definitions monitor: Use the IEC binary prefix definitions cutils: Do not include "qemu/units.h" directly hw/rdma: Use the IEC binary prefix definitions hw/virtio: Use the IEC binary prefix definitions hw/vfio: Use the IEC binary prefix definitions hw/sd: Use the IEC binary prefix definitions hw/usb: Use the IEC binary prefix definitions hw/net: Use the IEC binary prefix definitions hw/i386: Use the IEC binary prefix definitions hw/ppc: Use the IEC binary prefix definitions hw/mips: Use the IEC binary prefix definitions hw/mips/r4k: Constify params_size ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-03target/openrisc: Increase the TLB sizeRichard Henderson3-6/+7
The architecture supports 128 TLB entries. There is no reason not to provide all of them. In the process we need to fix a bug that failed to parameterize the configuration register that tells the operating system the number of entries. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com> --- v2: - Change VMState version.
2018-07-03target/openrisc: Stub out handle_mmu_fault for softmmuRichard Henderson1-30/+5
This hook is only used by CONFIG_USER_ONLY. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Use identical sizes for ITLB and DTLBRichard Henderson4-18/+16
The sizes are already the same, however, we can improve things if they are identical by design. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Fix cpu_mmu_indexRichard Henderson6-32/+49
The code in cpu_mmu_index does not properly honor SR_DME. This bug has workarounds elsewhere in that we flush the tlb more often than necessary, on the state changes that should be reflected in a change of mmu_index. Fixing this means that we can respect the mmu_index that is given to tlb_flush. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Fix tlb flushing in mtsprRichard Henderson1-6/+15
The previous code was confused, avoiding the flush of the old entry if the new entry is invalid. We need to flush the old page if the old entry is valid and the new page if the new entry is valid. This bug was masked by over-flushing elsewhere. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Reduce tlb to a single dimensionRichard Henderson4-32/+30
While we had defines for *_WAYS, we didn't define more than 1. Reduce the complexity by eliminating this unused dimension. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Merge mmu_helper.c into mmu.cRichard Henderson3-41/+12
With tlb_fill in mmu.c, we can simplify things further. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Remove indirect function calls for mmuRichard Henderson7-119/+32
There is no reason to use an indirect branch instead of simply testing the SR bits that control mmu state. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Merge tlb allocation into CPUOpenRISCStateRichard Henderson6-49/+46
There is no reason to allocate this separately. This was probably copied from target/mips which makes the same mistake. While doing so, move tlb into the clear-on-reset range. While not all of the TLB bits are guaranteed zero on reset, all of the valid bits are cleared, and the rest of the bits are unspecified. Therefore clearing the whole of the TLB is correct. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Form the spr index from tcgRichard Henderson3-15/+14
Rather than pass base+offset to the helper, pass the full index. In most cases the base is r0 and optimization yields a constant. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Exit the TB after l.mtsprRichard Henderson1-1/+16
A store to SR changes interrupt state, which should return to the main loop to recognize that state. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Split out is_userRichard Henderson1-15/+12
This allows us to limit the amount of ifdefs and isolate the test for usermode. Reviewed-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Link more translation blocksRichard Henderson1-41/+55
Track direct jumps via dc->jmp_pc_imm. Use that in preference to jmp_pc when possible. Emit goto_tb in that case, and lookup_and_goto_tb otherwise. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Fix singlestep_enabledRichard Henderson1-18/+17
We failed to store to cpu_pc before raising the exception, which caused us to re-execute the same insn that we stepped. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTBRichard Henderson2-5/+4
No need to use the interrupt mechanisms when we can simply exit the tb directly. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMPRichard Henderson1-4/+0
These values are unused. Reviewed-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Log interruptsRichard Henderson1-5/+25
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Add print_insn_or1kRichard Henderson5-115/+179
Rather than emit disassembly while translating, reuse the generated decoder to build a separate disassembler. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-02i386/monitor.c: make addresses canonical for "info mem" and "info tlb"Doug Gale1-32/+44
Correct the output of the "info mem" and "info tlb" monitor commands to correctly show canonical addresses. In 48-bit addressing mode, the upper 16 bits of linear addresses are equal to bit 47. In 57-bit addressing mode (LA57), the upper 7 bits of linear addresses are equal to bit 56. Signed-off-by: Doug Gale <doug16k@gmail.com> Message-Id: <20180617084025.29198-1-doug16k@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2024-12-25 20:45:35 +0000