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2023-05-18Hexagon (target/hexagon) Add overrides for loop setup instructionsTaylor Simpson2-0/+65
2023-05-18Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_writeTaylor Simpson6-12/+14
2023-05-18Hexagon (target/hexagon) Add v73 scalar instructionsTaylor Simpson4-1/+13
2023-05-18Hexagon (target/hexagon) Add v69 HVX instructionsTaylor Simpson4-0/+68
2023-05-18Hexagon (target/hexagon) Add v68 HVX instructionsTaylor Simpson3-3/+295
2023-05-18Hexagon (target/hexagon) Add v68 scalar instructionsTaylor Simpson6-6/+63
2023-05-18Hexagon (target/hexagon) Add support for v68/v69/v71/v73Taylor Simpson3-8/+18
2023-05-11target/loongarch: Do not include tcg-ldst.hRichard Henderson2-2/+0
2023-05-11target/sh4: Use MO_ALIGN where requiredRichard Henderson1-36/+66
2023-05-11target/nios2: Remove TARGET_ALIGNED_ONLYRichard Henderson1-0/+10
2023-05-11target/mips: Use MO_ALIGN instead of 0Richard Henderson1-1/+1
2023-05-11target/mips: Add missing default_tcg_memop_maskRichard Henderson4-28/+42
2023-05-11target/mips: Add MO_ALIGN to gen_llwp, gen_scwpRichard Henderson1-2/+3
2023-05-11target/m68k: Fix gen_load_fp for OS_LONGRichard Henderson1-0/+1
2023-05-10target/loongarch: Terminate vmstate subsections listRichard Henderson1-0/+1
2023-05-08target/i386: Add EPYC-Genoa model to support Zen 4 processor seriesBabu Moger1-0/+122
2023-05-08target/i386: Add VNMI and automatic IBRS feature bitsBabu Moger2-2/+5
2023-05-08target/i386: Add missing feature bits in EPYC-Milan modelBabu Moger1-0/+70
2023-05-08target/i386: Add feature bits for CPUID_Fn80000021_EAXBabu Moger2-0/+32
2023-05-08target/i386: Add a couple of feature bits in 8000_0008_EBXBabu Moger2-2/+6
2023-05-08target/i386: Add new EPYC CPU versions with updated cache_infoMichael Roth1-0/+118
2023-05-08target/i386: allow versioned CPUs to specify new cache_infoMichael Roth1-3/+32
2023-05-06Merge tag 'pull-loongarch-20230506' of https://gitlab.com/gaosong/qemu into s...Richard Henderson18-55/+9986
2023-05-06target/loongarch: CPUCFG support LSXSong Gao1-0/+1
2023-05-06target/loongarch: Use {set/get}_gpr replace to cpu_fprSong Gao5-43/+129
2023-05-06target/loongarch: Implement vldiSong Gao3-0/+148
2023-05-06target/loongarch: Implement vld vstSong Gao4-0/+239
2023-05-06target/loongarch: Implement vilvl vilvh vextrins vshufSong Gao5-0/+248
2023-05-06target/loongarch: Implement vreplve vpack vpickSong Gao5-0/+319
2023-05-06target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vrSong Gao3-0/+173
2023-05-06target/loongarch: Implement vbitsel vsetSong Gao5-0/+174
2023-05-06target/loongarch: Implement vfcmpSong Gao5-0/+190
2023-05-06target/loongarch: Implement vseq vsle vsltSong Gao5-0/+332
2023-05-06target/loongarch: Implement LSX fpu fcvt instructionsSong Gao5-0/+600
2023-05-06target/loongarch: Implement LSX fpu arith instructionsSong Gao8-1/+377
2023-05-06target/loongarch: Implement vfrstpSong Gao5-0/+61
2023-05-06target/loongarch: Implement vbitclr vbitset vbitrevSong Gao5-0/+437
2023-05-06target/loongarch: Implement vpcntSong Gao5-0/+38
2023-05-06target/loongarch: Implement vclo vclzSong Gao5-0/+67
2023-05-06target/loongarch: Implement vssrlrn vssrarnSong Gao5-0/+478
2023-05-06target/loongarch: Implement vssrln vssranSong Gao5-0/+499
2023-05-06target/loongarch: Implement vsrlrn vsrarnSong Gao5-0/+190
2023-05-06target/loongarch: Implement vsrln vsranSong Gao5-0/+179
2023-05-06target/loongarch: Implement vsrlr vsrarSong Gao5-0/+176
2023-05-06target/loongarch: Implement vsllwil vextlSong Gao5-0/+89
2023-05-06target/loongarch: Implement vsll vsrl vsra vrotrSong Gao3-0/+108
2023-05-06target/loongarch: Implement LSX logic instructionsSong Gao5-0/+94
2023-05-06target/loongarch: Implement vmskltz/vmskgez/vmsknzSong Gao5-0/+141
2023-05-06target/loongarch: Implement vsigncovSong Gao5-0/+75
2023-05-06target/loongarch: Implement vexthSong Gao5-0/+82