index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
Age
Commit message (
Expand
)
Author
Files
Lines
2020-07-02
target/riscv: vector floating-point classify instructions
LIU Zhiwei
6
-30
/
+107
2020-07-02
target/riscv: vector floating-point compare instructions
LIU Zhiwei
4
-0
/
+258
2020-07-02
target/riscv: vector floating-point sign-injection instructions
LIU Zhiwei
4
-0
/
+118
2020-07-02
target/riscv: vector floating-point min/max instructions
LIU Zhiwei
4
-0
/
+50
2020-07-02
target/riscv: vector floating-point square-root instruction
LIU Zhiwei
4
-0
/
+93
2020-07-02
target/riscv: vector widening floating-point fused multiply-add instructions
LIU Zhiwei
4
-0
/
+126
2020-07-02
target/riscv: vector single-width floating-point fused multiply-add instructions
LIU Zhiwei
4
-0
/
+334
2020-07-02
target/riscv: vector widening floating-point multiply
LIU Zhiwei
4
-0
/
+33
2020-07-02
target/riscv: vector single-width floating-point multiply/divide instructions
LIU Zhiwei
4
-0
/
+77
2020-07-02
target/riscv: vector widening floating-point add/subtract instructions
LIU Zhiwei
4
-0
/
+257
2020-07-02
target/riscv: vector single-width floating-point add/subtract instructions
LIU Zhiwei
4
-0
/
+250
2020-07-02
target/riscv: vector narrowing fixed-point clip instructions
LIU Zhiwei
4
-0
/
+168
2020-07-02
target/riscv: vector single-width scaling shift instructions
LIU Zhiwei
4
-0
/
+148
2020-07-02
target/riscv: vector widening saturating scaled multiply-add
LIU Zhiwei
4
-0
/
+243
2020-07-02
target/riscv: vector single-width fractional multiply with rounding and satur...
LIU Zhiwei
4
-0
/
+122
2020-07-02
target/riscv: vector single-width averaging add and subtract
LIU Zhiwei
4
-0
/
+129
2020-07-02
target/riscv: vector single-width saturating add and subtract
LIU Zhiwei
4
-0
/
+444
2020-07-02
target/riscv: vector integer merge and move instructions
LIU Zhiwei
4
-0
/
+225
2020-07-02
target/riscv: vector widening integer multiply-add instructions
LIU Zhiwei
4
-0
/
+83
2020-07-02
target/riscv: vector single-width integer multiply-add instructions
LIU Zhiwei
4
-0
/
+139
2020-07-02
target/riscv: vector widening integer multiply instructions
LIU Zhiwei
4
-0
/
+84
2020-07-02
target/riscv: vector integer divide instructions
LIU Zhiwei
4
-0
/
+125
2020-07-02
target/riscv: vector single-width integer multiply instructions
LIU Zhiwei
4
-0
/
+214
2020-07-02
target/riscv: vector integer min/max instructions
LIU Zhiwei
4
-0
/
+122
2020-07-02
target/riscv: vector integer comparison instructions
LIU Zhiwei
4
-0
/
+246
2020-07-02
target/riscv: vector narrowing integer right shift instructions
LIU Zhiwei
4
-0
/
+123
2020-07-02
target/riscv: vector single-width bit shift instructions
LIU Zhiwei
4
-0
/
+165
2020-07-02
target/riscv: vector bitwise logical instructions
LIU Zhiwei
4
-0
/
+96
2020-07-02
target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
LIU Zhiwei
4
-0
/
+294
2020-07-02
target/riscv: vector widening integer add and subtract
LIU Zhiwei
4
-0
/
+362
2020-07-02
target/riscv: vector single-width integer add and subtract
LIU Zhiwei
4
-0
/
+509
2020-07-02
target/riscv: add vector amo operations
LIU Zhiwei
6
-0
/
+339
2020-07-02
target/riscv: add fault-only-first unit stride load
LIU Zhiwei
4
-0
/
+212
2020-07-02
target/riscv: add vector index load and store instructions
LIU Zhiwei
4
-0
/
+293
2020-07-02
target/riscv: add vector stride load and store instructions
LIU Zhiwei
6
-0
/
+914
2020-07-02
target/riscv: add an internals.h header
LIU Zhiwei
1
-0
/
+24
2020-07-02
target/riscv: add vector configure instruction
LIU Zhiwei
7
-12
/
+210
2020-07-02
target/riscv: support vector extension csr
LIU Zhiwei
2
-1
/
+89
2020-07-02
target/riscv: implementation-defined constant parameters
LIU Zhiwei
2
-0
/
+12
2020-07-02
target/riscv: add vector extension field in CPURISCVState
LIU Zhiwei
2
-1
/
+14
2020-06-27
hw/mips: Implement the kvm_type() hook in MachineClass
Huacai Chen
2
-0
/
+37
2020-06-26
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200626'...
Peter Maydell
21
-857
/
+4141
2020-06-26
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell
5
-216
/
+1319
2020-06-26
i386: Mask SVM features if nested SVM is disabled
Eduardo Habkost
1
-0
/
+4
2020-06-26
kvm: i386: allow TSC to differ by NTP correction bounds without TSC scaling
Marcelo Tosatti
1
-5
/
+41
2020-06-26
target/i386: Add notes for versioned CPU models
Tao Xu
1
-0
/
+5
2020-06-26
target/i386: reimplement fpatan using floatx80 operations
Joseph Myers
1
-4
/
+483
2020-06-26
target/i386: reimplement fyl2x using floatx80 operations
Joseph Myers
1
-111
/
+262
2020-06-26
target/i386: reimplement fyl2xp1 using floatx80 operations
Joseph Myers
1
-9
/
+202
2020-06-26
target/i386: reimplement fprem, fprem1 using floatx80 operations
Joseph Myers
1
-108
/
+48
[next]