riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-05-29	spapr/xive: add KVM support	Cédric Le Goater	2	-0/+13
2019-05-29	target/ppc: Use vector variable shifts for VSL, VSR, VSRA	Richard Henderson	3	-61/+12
2019-05-29	target/ppc: Fix xvabs[sd]p, xvnabs[sd]p, xvneg[sd]p, xvcpsgn[sd]p	Anton Blanchard	1	-2/+2
2019-05-29	target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_VECTOR_LOAD_STORE	Anton Blanchard	1	-10/+58
2019-05-29	target/ppc: Fix xxspltib	Anton Blanchard	1	-4/+4
2019-05-29	target/ppc: Fix vsum2sws	Anton Blanchard	1	-1/+1
2019-05-29	target/ppc: Fix vslv and vsrv	Anton Blanchard	1	-7/+7
2019-05-29	target/ppc: Fix xxbrq, xxbrw	Anton Blanchard	1	-2/+2
2019-05-29	target/ppc: Fix xvxsigdp	Anton Blanchard	1	-1/+1
2019-05-29	target/ppc/kvm: Fix trace typo	Boxuan Li	2	-2/+2
2019-05-28	Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-280519-2...	Peter Maydell	13	-62/+79
2019-05-28	Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-may-19-2019-v...	Peter Maydell	6	-202/+674
2019-05-28	target/mips: convert UHI_plog to use common semihosting code	Alex Bennée	1	-6/+6
2019-05-28	target/mips: only build mips-semi for softmmu	Alex Bennée	3	-1/+12
2019-05-28	target/arm: correct return values for WRITE/READ in arm-semi	Alex Bennée	1	-8/+12
2019-05-28	target/arm: add LOG_UNIMP messages to arm-semi	Alex Bennée	1	-2/+3
2019-05-28	target/arm: use the common interface for WRITE0/WRITEC in arm-semi	Alex Bennée	1	-25/+4
2019-05-28	target/arm: fixup some of the commentary for arm-semi	Alex Bennée	1	-9/+31
2019-05-28	semihosting: move semihosting configuration into its own directory	Alex Bennée	11	-11/+11
2019-05-26	target/mips: realign comments to fix checkpatch warnings	Jules Irenge	1	-12/+22
2019-05-26	target/mips: add or remove space to fix checkpatch errors	Jules Irenge	1	-81/+94
2019-05-26	mips: Decide to map PAGE_EXEC in map_address	Jakub Jermář	1	-5/+8
2019-05-26	target/mips: Refactor and fix INSERT.<B\|H\|W\|D> instructions	Mateja Marjanovic	3	-18/+71
2019-05-26	target/mips: Refactor and fix COPY_U.<B\|H\|W> instructions	Mateja Marjanovic	3	-21/+59
2019-05-26	target/mips: Refactor and fix COPY_S.<B\|H\|W\|D> instructions	Mateja Marjanovic	3	-21/+67
2019-05-26	target/mips: Fix MSA instructions ST.<B\|H\|W\|D> on big endian host	Mateja Marjanovic	1	-20/+180
2019-05-26	target/mips: Fix MSA instructions LD.<B\|H\|W\|D> on big endian host	Mateja Marjanovic	1	-20/+168
2019-05-26	target/mips: Make the results of MOD_<U\|S>.<B\|H\|W\|D> the same as on hardware	Mateja Marjanovic	1	-2/+2
2019-05-26	target/mips: Make the results of DIV_<U\|S>.<B\|H\|W\|D> the same as on hardware	Mateja Marjanovic	1	-2/+3
2019-05-24	target/riscv: Only flush TLB if SATP.ASID changes	Jonathan Behrens	1	-1/+3
2019-05-24	target/riscv: More accurate handling of `sip` CSR	Jonathan Behrens	1	-2/+5
2019-05-24	target/riscv: Add checks for several RVC reserved operands	Richard Henderson	2	-3/+14
2019-05-24	target/riscv: Add the HGATP register masks	Alistair Francis	1	-0/+11
2019-05-24	target/riscv: Add the HSTATUS register masks	Alistair Francis	1	-0/+18
2019-05-24	target/riscv: Add Hypervisor CSR macros	Alistair Francis	1	-3/+6
2019-05-24	target/riscv: Allow setting mstatus virtulisation bits	Alistair Francis	1	-9/+8
2019-05-24	target/riscv: Add the MPV and MTL mstatus bits	Alistair Francis	1	-3/+2
2019-05-24	target/riscv: Improve the scause logic	Alistair Francis	1	-1/+1
2019-05-24	target/riscv: Trigger interrupt on MIP update asynchronously	Alistair Francis	2	-8/+27
2019-05-24	target/riscv: Mark privilege level 2 as reserved	Alistair Francis	1	-1/+1
2019-05-24	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis	2	-0/+16
2019-05-24	target/riscv: Create settable CPU properties	Alistair Francis	2	-0/+57
2019-05-24	target/riscv: Remove spaces from register names	Richard Henderson	1	-8/+8
2019-05-24	target/riscv: Split gen_arith_imm into functional and temp	Richard Henderson	2	-9/+24
2019-05-24	target/riscv: Split RVC32 and RVC64 insns into separate files	Richard Henderson	6	-151/+67
2019-05-24	target/riscv: Use pattern groups in insn16.decode	Richard Henderson	3	-69/+29
2019-05-24	target/riscv: Merge argument decode for RVC shifti	Richard Henderson	3	-53/+12
2019-05-24	target/riscv: Merge argument sets for insn32 and insn16	Richard Henderson	2	-170/+58
2019-05-24	target/riscv: Use --static-decode for decodetree	Richard Henderson	2	-7/+4
2019-05-24	target/riscv: Name the argument sets for all of insn32 formats	Richard Henderson	2	-3/+25