riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-05-29	target-microblaze: Bypass MMU with MMU_NOMMU_IDX	Edgar E. Iglesias	1	-1/+2
2018-05-29	target-microblaze: Conditionalize setting of PVR11_USE_MMU	Edgar E. Iglesias	1	-1/+2
2018-05-29	target-microblaze: Remove USE_MMU PVR checks	Edgar E. Iglesias	1	-11/+1
2018-05-29	target-microblaze: Tighten up TCGv_i32 vs TCGv type usage	Edgar E. Iglesias	2	-288/+295
2018-05-29	target-microblaze: Correct the PVR array size	Edgar E. Iglesias	1	-1/+1
2018-05-29	target-microblaze: Correct special register array sizes	Edgar E. Iglesias	2	-5/+4
2018-05-29	target-microblaze: Fallback to our latest CPU version	Edgar E. Iglesias	1	-2/+7
2018-05-29	target-microblaze: compute_ldst_addr: Use bool instead of int	Edgar E. Iglesias	1	-5/+5
2018-05-29	target-microblaze: dec_store: Use bool instead of unsigned int	Edgar E. Iglesias	1	-3/+4
2018-05-29	target-microblaze: dec_load: Use bool instead of unsigned int	Edgar E. Iglesias	1	-3/+4
2018-05-24	Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging	Peter Maydell	4	-13/+3
2018-05-24	Merge remote-tracking branch 'remotes/mwalle/tags/lm32-queue/20180521' into s...	Peter Maydell	1	-0/+4
2018-05-23	x86/cpu: use standard-headers/asm-x86.kvm_para.h	Michael S. Tsirkin	4	-13/+3
2018-05-21	i386: define the AMD 'virt-ssbd' CPUID feature bit (CVE-2018-3639)	Konrad Rzeszutek Wilk	1	-1/+1
2018-05-21	i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639)	Konrad Rzeszutek Wilk	3	-2/+36
2018-05-21	i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639)	Daniel P. Berrangé	2	-1/+2
2018-05-21	lm32: take BQL before writing IP/IM register	Michael Walle	1	-0/+4
2018-05-21	Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into st...	Peter Maydell	10	-188/+64
2018-05-20	Remove unnecessary variables for function return value	Laurent Vivier	8	-186/+62
2018-05-20	tcg: fix s/compliment/complement/ typos	Emilio G. Cota	2	-2/+2
2018-05-18	target/xtensa: Honor CPU_DUMP_FPU	Richard Henderson	1	-1/+2
2018-05-18	target/unicore32: Honor CPU_DUMP_FPU	Richard Henderson	1	-1/+3
2018-05-18	target/sparc: Honor CPU_DUMP_FPU	Richard Henderson	1	-7/+10
2018-05-18	target/s390x: Honor CPU_DUMP_FPU	Richard Henderson	1	-11/+12
2018-05-18	target/riscv: Honor CPU_DUMP_FPU	Richard Henderson	1	-5/+7
2018-05-18	target/ppc: Honor CPU_DUMP_FPU	Richard Henderson	1	-7/+13
2018-05-18	target/mips: Honor CPU_DUMP_FPU	Richard Henderson	1	-1/+2
2018-05-18	target/alpha: Honor CPU_DUMP_FPU	Richard Henderson	1	-9/+8
2018-05-18	target/arm: Implement SVE Permute - Extract Group	Richard Henderson	4	-0/+124
2018-05-18	target/arm: Implement SVE Integer Wide Immediate - Predicated Group	Richard Henderson	4	-1/+224
2018-05-18	target/arm: Implement SVE Bitwise Immediate Group	Richard Henderson	2	-0/+66
2018-05-18	target/arm: Implement SVE Element Count Group	Richard Henderson	4	-1/+465
2018-05-18	target/arm: Implement SVE floating-point trig select coefficient	Richard Henderson	4	-0/+72
2018-05-18	target/arm: Implement SVE floating-point exponential accelerator	Richard Henderson	4	-0/+125
2018-05-18	target/arm: Implement SVE Compute Vector Address Group	Richard Henderson	4	-0/+93
2018-05-18	target/arm: Implement SVE Bitwise Shift - Unpredicated Group	Richard Henderson	4	-0/+153
2018-05-18	target/arm: Implement SVE Stack Allocation Group	Richard Henderson	2	-0/+39
2018-05-18	target/arm: Implement SVE Index Generation Group	Richard Henderson	4	-0/+138
2018-05-18	target/arm: Implement SVE Integer Arithmetic - Unpredicated Group	Richard Henderson	2	-0/+47
2018-05-18	target/arm: Implement SVE Integer Multiply-Add Group	Richard Henderson	4	-0/+126
2018-05-18	target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group	Richard Henderson	4	-0/+323
2018-05-18	target/arm: Implement SVE bitwise shift by wide elements (predicated)	Richard Henderson	4	-0/+86
2018-05-18	target/arm: Implement SVE bitwise shift by vector (predicated)	Richard Henderson	4	-0/+64
2018-05-18	target/arm: Implement SVE bitwise shift by immediate (predicated)	Richard Henderson	4	-0/+445
2018-05-18	target/arm: Implement SVE Integer Reduction Group	Richard Henderson	4	-0/+225
2018-05-18	target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group	Richard Henderson	4	-0/+449
2018-05-18	target/arm: Implement SVE Predicate Misc Group	Richard Henderson	5	-0/+331
2018-05-18	target/arm: Implement SVE Predicate Logical Operations Group	Richard Henderson	5	-1/+429
2018-05-18	target/arm: Implement SVE predicate test	Richard Henderson	6	-1/+171
2018-05-18	target/arm: Implement SVE load vector/predicate	Richard Henderson	2	-0/+147