aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Collapse)AuthorFilesLines
2017-09-29console: purge curses bits from console.hGerd Hoffmann1-0/+6
Handle the translation from vga chars to curses chars in curses_update() instead of console_write_ch(). Purge any curses support bits from ui/console.h include file. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20170927103811.19249-1-kraxel@redhat.com
2017-09-27Merge remote-tracking branch ↵Peter Maydell5-6/+17
'remotes/dgilbert/tags/pull-migration-20170927a' into staging Migration pull 2017-09-27 # gpg: Signature made Wed 27 Sep 2017 14:56:23 BST # gpg: using RSA key 0x0516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert/tags/pull-migration-20170927a: migration: Route more error paths migration: Route errors up through vmstate_save migration: wire vmstate_save_state errors up to vmstate_subsection_save migration: Check field save returns migration: check pre_save return in vmstate_save_state migration: pre_save return int migration: disable auto-converge during bulk block migration Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-27Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.11-20170927' ↵Peter Maydell6-324/+72
into staging ppc patch queue 2017-09-27 Contains * a number of Mac machine type fixes * a number of embedded machine type fixes (preliminary to adding the Sam460ex board) * a important fix for handling of migration with KVM PR * assorted other minor fixes and cleanups # gpg: Signature made Wed 27 Sep 2017 08:40:48 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.11-20170927: (26 commits) macio: use object link between MACIO_IDE and MAC_DBDMA object macio: pass channel into MACIOIDEState via qdev property mac_dbdma: remove DBDMA_init() function mac_dbdma: QOMify mac_dbdma: remove unused IO fields from DBDMAState spapr: fix the value of SDR1 in kvmppc_put_books_sregs() ppc/pnv: check for OPAL firmware file presence ppc: remove all unused CPU definitions ppc: remove unused CPU definitions spapr_pci: make index property mandatory macio: convert pmac_ide_ops from old_mmio ppc/pnv: Improve macro parenthesization spapr: introduce helpers to migrate HPT chunks and the end marker ppc/kvm: generalize the use of kvmppc_get_htab_fd() ppc/kvm: change kvmppc_get_htab_fd() to return -errno on error ppc: Fix OpenPIC model ppc/ide/macio: Add missing registers ppc/mac: More rework of the DBDMA emulation ppc/mac: Advertise a high clock frequency for NewWorld Macs ppc: QOMify g3beige machine ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-27migration: pre_save return intDr. David Alan Gilbert5-6/+17
Modify the pre_save method on VMStateDescription to return an int rather than void so that it potentially can fail. Changed zillions of devices to make them return 0; the only case I've made it return non-0 is hw/intc/s390_flic_kvm.c that already had an error_report/return case. Note: If you add an error exit in your pre_save you must emit an error_report to say why. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20170925112917.21340-2-dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-09-27s390x/cpumodel: remove ais from z14 default model-> also for 2.10.1Christian Borntraeger1-1/+0
We disabled ais for 2.10, so let's also remove it from the z14 default model. Fixes: 3f2d07b3b01e ("s390x/ais: for 2.10 stable: disable ais facility") CC: qemu-stable@nongnu.org Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20170927072030.35737-2-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-27spapr: fix the value of SDR1 in kvmppc_put_books_sregs()Greg Kurz3-31/+8
When running with KVM PR, if a new HPT is allocated we need to inform KVM about the HPT address and size. This is currently done by hacking the value of SDR1 and pushing it to KVM in several places. Also, migration breaks the guest since it is very unlikely the HPT has the same address in source and destination, but we push the incoming value of SDR1 to KVM anyway. This patch introduces a new virtual hypervisor hook so that the spapr code can provide the correct value of SDR1 to be pushed to KVM each time kvmppc_put_books_sregs() is called. It allows to get rid of all the hacking in the spapr/kvmppc code and it fixes migration of nested KVM PR. Suggested-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc: remove all unused CPU definitionsJohn Snow1-225/+0
Remove *all* unused CPU definitions as indicated by compile-time `#if 0` constructs. Signed-off-by: John Snow <jsnow@redhat.com> [dwg: Removed some additional now-useless comments] Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc: remove unused CPU definitionsJohn Snow1-32/+0
Following commit aef77960, remove now-unused definitions from cpu-models.h. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc/kvm: generalize the use of kvmppc_get_htab_fd()Greg Kurz2-20/+11
The use of KVM_PPC_GET_HTAB_FD is open-coded in kvmppc_read_hptes() and kvmppc_write_hpte(). This patch modifies kvmppc_get_htab_fd() so that it can be used everywhere we need to access the in-kernel htab: - add an index argument => only kvmppc_read_hptes() passes an actual index, all other users pass 0 - add an errp argument to propagate error messages to the caller. => spapr migration code prints the error => hpte helpers pass &error_abort to keep the current behavior of hw_error() While here, this also fixes a bug in kvmppc_write_hpte() so that it opens the htab fd for writing instead of reading as it currently does. This never broke anything because we currently never call this code, as explained in the changelog of commit c1385933804bb: "This support updating htab managed by the hypervisor. Currently we don't have any user for this feature. This actually bring the store_hpte interface in-line with the load_hpte one. We may want to use this when we want to emulate henter hcall in qemu for HV kvm." The above is still true today. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc/kvm: change kvmppc_get_htab_fd() to return -errno on errorGreg Kurz1-2/+8
When kvmppc_get_htab_fd() fails, its return value is propagated up to qemu_savevm_state_iterate() or to qemu_savevm_state_complete_precopy(). All savevm handlers expect to receive a negative errno on error. Let's patch kvmppc_get_htab_fd() accordingly. While here, let's change htab_load() in the spapr code to also propagate the error, since it doesn't make sense to abort() if we couldn't get the htab fd from KVM. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc: Add 460EX embedded CPUBALATON Zoltan3-0/+42
Despite its name it is a 440 core CPU Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc/kvm: drop kvmppc_has_cap_htab_fd()Greg Kurz2-11/+0
It never got used since its introduction (commit 7c43bca004af). Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc/kvm: check some capabilities with kvm_vm_check_extension()Greg Kurz1-3/+3
The following capabilities are VM specific: - KVM_CAP_PPC_SMT_POSSIBLE - KVM_CAP_PPC_HTAB_FD - KVM_CAP_PPC_ALLOC_HTAB If both KVM HV and KVM PR are present, checking them always return the HV value, even if we explicitely requested to use PR. This has no visible effect for KVM_CAP_PPC_ALLOC_HTAB, because we also try the KVM_PPC_ALLOCATE_HTAB ioctl which is only suppored by HV. As a consequence, the spapr code doesn't even check KVM_CAP_PPC_HTAB_FD. However, this will cause kvmppc_hint_smt_possible(), introduced by commit fa98fbfcdfcb9, to report several VSMT modes (eg, Available VSMT modes: 8 4 2 1) whereas PR only support mode 1. This patch fixes all three anyway to use kvm_vm_check_extension(). It is okay since the VM is already created at the time kvm_arch_init() or kvmppc_reset_htab() is called. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-26target/xtensa: Use the pre-defined MEMTXATTRS_UNSPECIFIED macroAlistair Francis1-2/+2
Instead of using the hardcoded (MemTxAttrs){0} for no memory attributes let's use the already defined MEMTXATTRS_UNSPECIFIED macro instead. This is technically a change of behaviour as MEMTXATTRS_UNSPECIFIED sets the unspecified field to 1, but it doesn't look like anything is checking this field. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-09-23Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2-10/+11
* Speed up AddressSpaceDispatch creation (Alexey) * Fix kvm.c assert (David) * Memory fixes and further speedup (me) * Persistent reservation manager infrastructure (me) * virtio-serial: add enable_backend callback (Pavel) * chardev GMainContext fixes (Peter) # gpg: Signature made Fri 22 Sep 2017 20:07:33 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (32 commits) chardev: remove context in chr_update_read_handler chardev: use per-dev context for io_add_watch_poll chardev: add Chardev.gcontext field chardev: new qemu_chr_be_update_read_handlers() scsi: add persistent reservation manager using qemu-pr-helper scsi: add multipath support to qemu-pr-helper scsi: build qemu-pr-helper scsi, file-posix: add support for persistent reservation management memory: Share special empty FlatView memory: seek FlatView sharing candidates among children subregions memory: trace FlatView creation and destruction memory: Create FlatView directly memory: Get rid of address_space_init_shareable memory: Rework "info mtree" to print flat views and dispatch trees memory: Do not allocate FlatView in address_space_init memory: Share FlatView's and dispatch trees between address spaces memory: Move address_space_update_ioeventfds memory: Alloc dispatch tree where topology is generared memory: Store physical root MR in FlatView memory: Rename mem_begin/mem_commit/mem_add helpers ... # Conflicts: # configure
2017-09-22s390x/ais: for 2.10 stable: disable ais facilityChristian Borntraeger1-2/+7
The migration interface for ais was introduced with kernel 4.13 but the capability itself had been active since 4.12. As migration support is considered necessary lets disable ais in the 2.10 stable version. A proper fix and re-enablement will be done for qemu 2.11. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20170921140834.14233-2-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-22memory: Get rid of address_space_init_shareableAlexey Kardashevskiy2-10/+11
Since FlatViews are shared now and ASes not, this gets rid of address_space_init_shareable(). This should cause no behavioural change. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20170921085110.25598-17-aik@ozlabs.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-09-21target/arm: Remove out of date ARM ARM section references in A64 decoderPeter Maydell1-113/+114
In the A64 decoder, we have a lot of references to section numbers from version A.a of the v8A ARM ARM (DDI0487). This version of the document is now long obsolete (we are currently on revision B.a), and various intervening versions renumbered all the sections. The most recent B.a version of the document doesn't assign section numbers at all to the individual instruction classes in the way that the various A.x versions did. The simplest thing to do is just to delete all the out of date C.x.x references. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20170915150849.23557-1-peter.maydell@linaro.org
2017-09-21nvic: Support banked exceptions in acknowledge and completePeter Maydell2-5/+18
Update armv7m_nvic_acknowledge_irq() and armv7m_nvic_complete_irq() to handle banked exceptions: * acknowledge needs to use the correct vector, which may be in sec_vectors[] * acknowledge needs to return to its caller whether the exception should be taken to secure or non-secure state * complete needs its caller to tell it whether the exception being completed is a secure one or not Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-20-git-send-email-peter.maydell@linaro.org
2017-09-21target/arm: Handle banking in negative-execution-priority check in ↵Peter Maydell1-5/+16
cpu_mmu_index() Now that we have a banked FAULTMASK register and banked exceptions, we can implement the correct check in cpu_mmu_index() for whether the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes handlers which have requested a negative execution priority to run with the MPU disabled. In v8M the test has to check this for the current security state and so takes account of banking. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-17-git-send-email-peter.maydell@linaro.org
2017-09-21nvic: Make set_pending and clear_pending take a secure parameterPeter Maydell2-11/+27
Make the armv7m_nvic_set_pending() and armv7m_nvic_clear_pending() functions take a bool indicating whether to pend the secure or non-secure version of a banked interrupt, and update the callsites accordingly. In most callsites we can simply pass the correct security state in; in a couple of cases we use TODO comments to indicate that we will return the code in a subsequent commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-10-git-send-email-peter.maydell@linaro.org
2017-09-21nvic: Implement AIRCR changes for v8MPeter Maydell2-0/+19
The Application Interrupt and Reset Control Register has some changes for v8M: * new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have real state if the security extension is implemented and otherwise are constant * the PRIGROUP field is banked between security states * non-secure code can be blocked from using the SYSRESET bit to reset the system if SYSRESETREQS is set Implement the new state and the changes to register read and write. For the moment we ignore the effects of the secure PRIGROUP. We will implement the effects of PRIS and BFHFNMIS later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-6-git-send-email-peter.maydell@linaro.org
2017-09-21target/arm: Implement MSR/MRS access to NS banked registersPeter Maydell1-0/+110
In v8M the MSR and MRS instructions have extra register value encodings to allow secure code to access the non-secure banked version of various special registers. (We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because we don't currently implement the stack limit registers at all.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-2-git-send-email-peter.maydell@linaro.org
2017-09-21mips: Improve macro parenthesizationEric Blake1-28/+28
Although none of the existing macro call-sites were broken, it's always better to write macros that properly parenthesize arguments that can be complex expressions, so that the intended order of operations is not broken. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: replace cpu_mips_init() with cpu_generic_init()Igor Mammedov2-19/+1
now cpu_mips_init() reimplements subset of cpu_generic_init() tasks, so just drop it and use cpu_generic_init() directly. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: use internal.h instead of cpu.h] Tested-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: MIPSCPU model subclassesIgor Mammedov5-64/+117
Register separate QOM types for each mips cpu model, so it would be possible to reuse generic CPU creation routines. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: use internal.h, use void* to hold cpu_def in MIPSCPUClass, mark MIPSCPU abstract, address Eduardo Habkost review] Tested-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: call cpu_mips_realize_env() from mips_cpu_realizefn()Philippe Mathieu-Daudé2-1/+3
This changes the order between cpu_mips_realize_env() and cpu_exec_initfn(), but cpu_exec_initfn() don't have anything that depends on cpu_mips_realize_env() being called first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Igor Mammedov <imammedo@redhat.com> Tested-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: split cpu_mips_realize_env() out of cpu_mips_init()Philippe Mathieu-Daudé2-7/+13
so it can be used in mips_cpu_realizefn() in the next commit Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Igor Mammedov <imammedo@redhat.com> Tested-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: introduce internal.h and cleanup cpu.hPhilippe Mathieu-Daudé11-353/+372
no logical change, only code movement (and fix a comment typo). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Igor Mammedov <imammedo@redhat.com> Tested-by: James Hogan <james.hogan@imgtec.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: move hw/mips/cputimer.c to target/mips/Philippe Mathieu-Daudé2-1/+165
This timer is a required part of the MIPS32/MIPS64 System Control coprocessor (CP0). Moving it with the other architecture related files will allow an opaque use of CPUMIPSState* in the next commit (introduce "internal.h"). also remove it from 'user' targets, remove an unnecessary include. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Igor Mammedov <imammedo@redhat.com> Tested-by: James Hogan <james.hogan@imgtec.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-20Merge remote-tracking branch ↵Peter Maydell4-4/+13
'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine/CPU/NUMA queue, 2017-09-19 # gpg: Signature made Tue 19 Sep 2017 21:17:01 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: MAINTAINERS: Update git URLs for my trees hw/acpi-build: Fix SRAT memory building in case of node 0 without RAM NUMA: Replace MAX_NODES with nb_numa_nodes in for loop numa: cpu: calculate/set default node-ids after all -numa CLI options are parsed arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly pc: use generic cpu_model parsing vl.c: convert cpu_model to cpu type and set of global properties before machine_init() cpu: make cpu_generic_init() abort QEMU on error qom: cpus: split cpu_generic_init() on feature parsing and cpu creation parts hostmem-file: Add "discard-data" option osdep: Define QEMU_MADV_REMOVE vl: Clean up user-creatable objects when exiting Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-19s390x/ccw: create s390 phb for compat reasons as wellCornelia Huck1-0/+3
d32bd032d8 ("s390x/ccw: create s390 phb conditionally") made registering the s390 pci host bridge conditional on presense of the zpci facility bit. Sadly, that breaks migration from machines that did not use the cpu model (2.7 and previous). Create the s390 phb for pre-cpu model machines as well: We can tweak s390_has_feat() to always indicate the zpci facility bit when no cpu model is available (on 2.7 and previous compat machines). Fixes: d32bd032d8 ("s390x/ccw: create s390 phb conditionally") Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: allow CPU hotplug in random core-id orderDavid Hildenbrand1-7/+1
SCLP correctly indicates the core-id aka. CPU address for each available CPU. As the core-id corresponds to cpu_index, also a newly created kvm vcpu gets assigned this core-id as vcpu id. So SIGP in the kernel works correctly (it uses the vcpu id to lookup the correct CPU). So there should be nothing hindering us from hotplugging CPUs in random core-id order. This now makes sure that the output from "query-hotpluggable-cpus" is completely true. Until now, a specific order is implicit. Performance vice, hotplugging CPUs in non-sequential order might not be the best thing to do, as VCPU lookup inside KVM might be a little slower. But that doesn't hinder us from supporting it. next_core_id is now used by linux user only. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-23-david@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: get rid of cpu_s390x_create()David Hildenbrand3-45/+3
Now that there is only one user of cpu_s390x_create() left, make cpu creation look like on x86. - Perform the model/properties split and checks in s390_init_cpus() - Parse features only once without having to remember if already parsed - Pass only the typename to s390x_new_cpu() - Use the typename of an existing CPU for hotplug via cpu-add Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-21-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: allow cpu hotplug via device_addDavid Hildenbrand1-0/+1
E.g. the following now works: device_add host-s390-cpu,id=cpu1,core-id=1 The system will perform the same checks as when using cpu_add: - If the core_id is already in use - If the next sequential core_id isn't used - If core-id >= max_cpu is specified In addition, mixed CPU models are checked. E.g. if starting with -cpu host and trying to hotplug "qemu-s390-cpu": "Mixed CPU models are not supported on s390x." Reviewed-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: print CPU definitions in sorted orderDavid Hildenbrand1-15/+41
Other architectures provide nicely sorted lists, let's do it similarly on s390x. While at it, clean up the code we have to touch either way. Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-16-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19target/s390x: rename next_cpu_id to next_core_idDavid Hildenbrand2-7/+6
Adapt to the new term "core_id". While at it, fix the type and drop the initialization to 0 (which is superfluous). Reviewed-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19target/s390x: use "core-id" for cpu number/address/id handlingDavid Hildenbrand7-65/+29
Some time ago we discussed that using "id" as property name is not the right thing to do, as it is a reserved property for other devices and will not work with device_add. Switch to the term "core-id" instead, and use it as an equivalent to "CPU address" mentioned in the PoP. There is no such thing as cpu number, so rename env.cpu_num to env.core_id. We use "core-id" as this is the common term to use for device_add later on (x86 and ppc). We can get rid of cpu->id now. Keep cpu_index and env->core_id in sync. cpu_index was already implicitly used by e.g. cpu_exists(), so keeping both in sync seems to be the right thing to do. cpu_index will now no longer automatically get set via cpu_exec_realizefn(). For now, we were lucky that both implicitly stayed in sync. Our new cpu property "core-id" can be a static property. Range checks can be avoided by using the correct type and the "setting after realized" check is done implicitly. device_add will later need the reserved "id" property. Hotplugging a CPU on s390x will then be: "device_add host-s390-cpu,id=cpu2,core-id=2". Reviewed-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19target/s390x: set cpu->id for linux user when realizingDavid Hildenbrand1-7/+4
scc->next_cpu_id is updated when realizing. Setting it just before that point looks cleaner. Reviewed-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19target/s390x: use program_interrupt() in per_check_exception()David Hildenbrand1-6/+9
Clean it up by reusing program_interrupt(). Add a concern regarding ilen. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19target/s390x: use trigger_pgm_exception() in s390_cpu_handle_mmu_fault()David Hildenbrand1-2/+1
This looks cleaner. linux-user will not use the ilen field, so setting it doesn't do any harm. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: move sclp_service_call() to sclp.hDavid Hildenbrand2-1/+1
Implemented in sclp.c, so let's move it to the right include file. Also adjust some includes. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-9-david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19target/s390x: move some s390x typedefs to cpu-qom.hDavid Hildenbrand3-7/+11
This allows us to drop inclusion of cpu_models.h in cpu-qom.h, and prepares for using cpu-qom.h as a s390 specific version of typedefs.h Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-8-david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: move subsystem_reset() to s390-virtio-ccw.hDavid Hildenbrand2-1/+1
Implemented in s390-virtio-ccw.c, so move it to the right header. We can also drop the extern. Fix up one include. Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x: move s390_virtio_hypercall() to s390-virtio-hcall.hDavid Hildenbrand3-1/+2
Implemented in hw/s390x/s390-virtio-hcall.c, so let's move it to the right header file. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19exec,dump,i386,ppc,s390x: don't include exec/cpu-all.h explicitlyDavid Hildenbrand5-5/+0
All but a handful of files include exec/cpu-all.h via cpu.h only. As these files already include cpu.h, let's just drop the additional include. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170913132417.24384-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x/pci: fixup ind_offset of msix routing entryYi Min Zhao1-3/+1
The guest uses the mpcifc instruction to register the aibvo of a zpci device, which is the starting offset of indicators in the indicator area and thus remains constant. Each msix vector is an offset from the aibvo. When we map a msix route to an adapter route, we should not modify the starting offset, but instead add the vector to the starting offset to get the absolute offset in the specific route. Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Message-Id: <1504606380-49341-3-git-send-email-zyimin@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19s390x/pci: remove idx from msix msg dataYi Min Zhao1-3/+7
PCIDevice pointer has been a parameter of kvm_arch_fixup_msi_route(). So we don't need to store zpci idx in msix message data to find out the specific zpci device. Instead, we could use pci device id to find its corresponding zpci device. Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Message-Id: <1504606380-49341-2-git-send-email-zyimin@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-09-19target/i386: fix "info mem" for LA57 modePaolo Bonzini1-4/+4
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-09-19hyperv: add header with protocol definitionsRoman Kagan6-51/+306
The definitions for Hyper-V emulation are currently taken from a header imported from the Linux kernel. However, as these describe a third-party protocol rather than a kernel API, it probably wasn't a good idea to publish it in the kernel uapi. This patch introduces a header that provides all the necessary definitions, superseding the one coming from the kernel. The new header supports (temporary) coexistence with the kernel one. The constants explicitly named in the Hyper-V specification (e.g. msr numbers) are defined in a non-conflicting way. Other constants and types have got new names. While at this, the protocol data structures are defined in a more conventional way, without bitfields, enums, and excessive unions. The code using this stuff is adjusted, too; it can now be built both with and without the kernel header in the tree. Signed-off-by: Roman Kagan <rkagan@virtuozzo.com> Message-Id: <20170713201522.13765-2-rkagan@virtuozzo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2024-12-23 20:27:09 +0000