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2022-01-21target/riscv: Relax UXL field for debuggingLIU Zhiwei1-4/+4
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei2-6/+25
2022-01-21target/riscv: Set default XLEN for hypervisorLIU Zhiwei1-0/+10
2022-01-21target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei1-1/+1
2022-01-21target/riscv: Adjust vector address with maskLIU Zhiwei1-10/+15
2022-01-21target/riscv: Fix check range for first fault onlyLIU Zhiwei1-2/+2
2022-01-21target/riscv: Remove VILL field in VTYPELIU Zhiwei1-1/+0
2022-01-21target/riscv: Adjust vsetvl according to XLENLIU Zhiwei2-2/+10
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei5-6/+19
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei3-23/+16
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei5-69/+21
2022-01-21target/riscv: Alloc tcg global for cur_pm[mask|base]LIU Zhiwei1-24/+8
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei5-0/+68
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei2-5/+10
2022-01-21target/riscv: Relax debug check for pm writeLIU Zhiwei1-0/+3
2022-01-21target/riscv: Use gdb xml according to max mxlenLIU Zhiwei2-24/+55
2022-01-21target/riscv: Extend pc for runtime pc writeLIU Zhiwei1-3/+19
2022-01-21target/riscv: Ignore the pc bits above XLENLIU Zhiwei1-1/+1
2022-01-21target/riscv: Create xl field in envLIU Zhiwei5-32/+46
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei4-9/+27
2022-01-21target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei2-6/+2
2022-01-21target/riscv: Don't save pc when exception returnLIU Zhiwei3-9/+6
2022-01-21target/riscv: Adjust pmpcfg access with mxlLIU Zhiwei2-8/+23
2022-01-21target/riscv: rvv-1.0: Allow Zve32f extension to be turned onFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insnsFrank Chang1-0/+3
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insnsFrank Chang1-0/+18
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insnsFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for scalar fp insnsFrank Chang1-0/+21
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for configuration insnsFrank Chang1-2/+2
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang5-4/+7
2022-01-21target/riscv: rvv-1.0: Allow Zve64f extension to be turned onFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insnsFrank Chang1-3/+6
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insnsFrank Chang1-7/+25
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insnsFrank Chang1-1/+2
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for scalar fp insnsFrank Chang1-10/+31
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insnsFrank Chang1-2/+25
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insnsFrank Chang1-6/+33
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for load and store insnsFrank Chang1-4/+15
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for configuration insnsFrank Chang1-2/+4
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang5-2/+16
2022-01-21target/riscv: Support virtual time context synchronizationYifei Jiang1-0/+30
2022-01-21target/riscv: Implement virtual time adjusting with vm state changingYifei Jiang1-0/+15
2022-01-21target/riscv: Add kvm_riscv_get/put_regs_timerYifei Jiang2-0/+79
2022-01-21target/riscv: Add host cpu typeYifei Jiang2-0/+16
2022-01-21target/riscv: Handle KVM_EXIT_RISCV_SBI exitYifei Jiang2-1/+113
2022-01-21target/riscv: Support setting external interrupt by KVMYifei Jiang4-1/+28
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang6-1/+75
2022-01-21target/riscv: Implement kvm_arch_put_registersYifei Jiang1-1/+103
2022-01-21target/riscv: Implement kvm_arch_get_registersYifei Jiang1-1/+111
2022-01-21target/riscv: Implement function kvm_arch_init_vcpuYifei Jiang1-1/+33
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